VLSI KoreaBaidu Kunlun Across Generations: From FPGA XPU to a 30,000-Accelerator AI Cloud
From FPGA XPU to Kunlun 3 and a 30,000-device cluster, how Baidu vertically integrated search, PaddlePaddle and cloud.
🆓 Free article · Anyone can read this article for free
This article is for readers comparing cloud AI accelerator architecture and system economics for purchasing, investment and supply-chain decisions. It separates peak specifications from model-level TCO and identifies the evidence that should validate the next generation.
Data cutoff: August 2, 2026
TL;DR
Kunlun is not simply the roadmap of an independent chip company. It is the product of a search and cloud operator vertically integrating production workloads, FPGA experience, ASICs, boards, clusters and PaddlePaddle. Baidu began FPGA acceleration research in 2010 and had deployed more than 10,000 boards by 2017. The resulting workload traces and compiler experience informed the first Kunlun, its second-generation product family and the third-generation XPU deployed in large cloud clusters.
The first-generation K200 used Samsung 14 nm and I-Cube 2.5D packaging with 16 GB of HBM, 512 GB/s, 256 INT8 TOPS and 150 W. The second generation moved to 7 nm, XPU-R cores and GDDR6 R-series products. The strongest third-generation evidence is deployment: Baidu says a 10,000-chip cluster began operating in early 2025 and a 30,000-chip cluster followed. Chip-level compute, memory and link data remain far less transparent than for TPU or Trainium.
The important questions are therefore whether PaddlePaddle and ERNIE map naturally to XPU, whether vendor-reported model FLOPS utilization and training efficiency survive independent definitions, and whether the proposed Kunlunxin separation can convert captive Baidu volume into recurring external revenue.
Generation map
| Generation | Process and memory | Public compute | Primary role | Deployment evidence |
|---|---|---|---|---|
| FPGA XPU | Programmable FPGA platforms | Workload-specific pipelines | Search, recommendation, NLP, image | More than 10,000 deployed by 2017 |
| Kunlun 1 K100/K200 | Samsung 14 nm, 2.5D, 16 GB HBM on K200 | 256 INT8 TOPS, 150 W on K200 | Datacenter inference and training | Mass production in 2020, about 20,000 units deployed |
| Kunlun 2 R-series | 7 nm, XPU-R, GDDR6 products | Vendor states 2x to 3x core uplift | Cloud inference and broader AI compute | Commercial cloud and server products |
| Kunlun 3 | XPU architecture, details not public | Not sufficiently disclosed | Large-model training and inference | 10,000-chip cluster in early 2025, 30,000-chip cluster later in 2025 |
| M100 and M300 | Details not public | Details not public | Next product roadmap | Announced, not comparable on public specifications |
The generation history follows Kunlunxin's official commercialization record. M100 and M300 have been announced but lack enough verified architecture and memory information for a quantitative comparison.
FPGA XPU: the real first generation
FPGAs are less efficient than ASICs but can be reconfigured as operators and tensor shapes change. For Baidu, their purpose was to learn what repeated in real search, recommendation, NLP and image traffic, where memory access stalled, and how compiler failures should fall back to services.
The XPU disclosed at Hot Chips in 2017 combined small programmable cores, tensor and vector engines, local memory, and software-defined instructions and scheduling. It sat between a general CPU and a fixed convolution engine. The deepest asset was a corpus of production graphs, shapes, quantization errors, latency tails and operator frequencies. Retaining programmability in the XPU layer reduced the risk that an ASIC would target a model that had changed by tape-out.
Kunlun 1: memory and workload on 14 nm
Kunlun 1 was disclosed in 2018, taped out in 2019 and reached mass production in 2020. Samsung officially identified its 14 nm process and I-Cube 2.5D package. K200 provided 16 GB of HBM at 512 GB/s, 256 INT8 TOPS at 150 W, plus FP16 and FP32 support.
The architecture combined command and scheduling cores, tensor and vector data paths and distributed local memory under software-defined neural-network instructions. It processed control and movement on chip rather than maximizing only a matrix engine.
Samsung and Baidu claimed roughly three times the performance of prior GPU and FPGA systems on ERNIE inference, but the workload conditions do not justify a universal comparison. Stronger evidence is Baidu's statement that approximately 20,000 units served search, recommendation and cloud workloads by 2020. Captive demand absorbed early yield and software imperfections.
Kunlun 2: from HBM chip to GDDR6 product family
The second generation moved to 7 nm and an XPU-R core described as two to three times the prior core's compute. Products expanded into R100, R200, RG800 and multi-card systems.
The move from HBM to GDDR6 is notable. HBM maximizes bandwidth and package density but raises interposer cost and supply dependence. GDDR6 requires more board routing and power but offers a broader supply base, flexible capacity and simpler packaging. For varied cloud inference, board BOM and availability may matter more than the highest bandwidth.
The choice is workload-dependent rather than a simple downgrade. Recommendation and inference can value capacity and request-level parallelism. Dense training can pay for lower bandwidth through additional cards and communication. PaddlePaddle and the XPU backend reduce adoption cost for Baidu's own models; external PyTorch users need compatibility and debugging of comparable quality.
Kunlun 3: cluster evidence before chip disclosure
Kunlunxin says the third generation commercialized in 2024. Baidu AI Cloud brought a 10,000-device third-generation cluster online in February 2025, then announced a 30,000-device cluster. Tianchi 512 supernodes combine through a scale-out fabric for trillion-parameter training.
Baidu reports 58% model FLOPS utilization, 98% effective training ratio and 90% bandwidth effectiveness on the 10,000-device system. Each metric depends on a definition, workload, precision, sequence, parallelism and observation window that are not fully public. They cannot be directly compared with another vendor's cluster.
The operational implication is still substantial. Keeping jobs alive at that scale requires collective software, topology-aware placement, checkpoints, device isolation, storage ingestion and power control. A 30,000-card cluster is unlikely to be one flat scale-up domain; the question is how many devices a single job can use efficiently and how quickly it recovers.
Public chip specifications remain sparse. Filling process, memory, precision or link fields from unofficial sources would create false precision and make customer capacity planning harder, not easier.
M100, M300 and the Kunlunxin separation
Baidu announced M100 and M300 without enough architecture and availability detail to call them quantified fourth and fifth generations. Evidence should come from boards, cloud instances, memory, links, supported precision and compiler releases.
In January 2026, Baidu proposed a spin-off and separate listing of Kunlunxin. An independent company can raise capital and sell beyond Baidu, but may weaken close workload co-design. The decisive indicator is customer concentration: recurring non-Baidu orders, production PyTorch workloads and a broader server-partner base.
The real moat and weakness
The moat is production workload history, PaddlePaddle and ERNIE control, and the option value of domestically available capacity under export controls. The weakness is transparency. When benchmarks, power, failure rates and specifications are incomplete, each customer must reproduce them in a paid proof of concept, lengthening the sales cycle.
Watch points
- Official process, memory, precision and link information for Kunlun 3.
- Single-job scale, workload definitions, fault rate and checkpoint overhead in the 30,000-device cluster.
- Actual cloud instances and server SKUs for M100 and M300.
- PyTorch, vLLM and popular-model operator coverage outside PaddlePaddle.
- Recurring external customers and service revenue after separation.
Contrarian read
Thirty thousand chips may signal low chip efficiency rather than an advantage. Compensating for compute or bandwidth with quantity increases network, power, cooling, spares and failure surface. A high reported MFU can coexist with weak rack-level output and total cost.
The opposite is also plausible. When demand exceeds accelerator supply and imported GPUs are constrained, a large pool of installed, functioning capacity is itself a moat. Search and ERNIE traffic can keep it utilized. An available cluster can be more valuable than a more efficient chip that cannot be obtained.
Korean lens
Korean NPU firms need workload and compiler traces before silicon. After the first generation, board BOM, memory choice, cluster software and switching cost matter more than an isolated peak. Without captive cloud, portal or telecom workloads, a fabless company cannot reproduce Baidu's learning loop alone.
HBM is not the only memory answer. GDDR6, GDDR7, CXL memory and advanced packaging can serve different cost envelopes, but a memory change requires rethinking arithmetic intensity, board power and collective topology.
Sources
- Kunlunxin core technology and generation history
- Samsung and Baidu Kunlun production announcement
- Hot Chips 32 Baidu Kunlun presentation
- Baidu Kunlun second-generation announcement
- Baidu AI Cloud Kunlun solution
- Baidu AI Cloud 10,000-chip cluster announcement
- Baidu AI Cloud 30,000-chip cluster and M100/M300 announcement
- Baidu proposed Kunlunxin spin-off
Disclosure
This article is for informational purposes only and does not constitute a recommendation to buy or sell any security. Figures and facts are based on publicly available corporate disclosures, media reports and market research, and errors may occur in the source material or writing process. The author may hold shares of companies mentioned. Readers are solely responsible for all investment decisions and outcomes.
