VLSI KoreaHuawei Ascend 310 to 970: Compensating for Process Constraints with a SuperPoD Strategy
How Huawei's Ascend 310-to-970 roadmap uses memory specialization and an 8,192-chip SuperPoD to offset process constraints.
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This article is for readers comparing cloud AI accelerator architecture and system economics for purchasing, investment and supply-chain decisions. It separates peak specifications from model-level TCO and identifies the evidence that should validate the next generation.
Data cutoff: August 2, 2026
TL;DR
Huawei Ascend is best read as system design under constraints, not as a single-chip benchmark. Ascend 310 brought Da Vinci and CANN to edge inference in 2018; Ascend 910 extended the stack to datacenter training in 2019. Ascend 910B and 910C now underpin deployed Chinese training and inference systems including Atlas 900 A3 and CloudMatrix384. Huawei has publicly acknowledged that access to advanced manufacturing nodes may remain constrained, so it links 384 910C devices through UnifiedBus 1.0 and proposes 8,192 Ascend 950DT devices over an all-optical UnifiedBus 2.0 domain.
In the 2025 roadmap, 950PR targets prefill and recommendation while 950DT targets decode and training with a different memory balance. Both target 1 PFLOPS at FP8, 2 PFLOPS at FP4 and 2 TB/s of interconnect; 950DT adds a proposed 144 GB, 4 TB/s proprietary HBM subsystem. Ascend 960 in 2027 and 970 in 2028 aim to double compute annually. The risk is not the roadmap arithmetic but volume, yield and effective performance across leading-node silicon, memory, optics, software and clusters containing thousands of NPUs.
Generation map
| Generation | Main role | Public architectural direction | System role | Status |
|---|---|---|---|---|
| Ascend 310 | Edge and inference | Da Vinci AI Core, low-power SoC family | Atlas edge and inference products | Launched in 2018 |
| Ascend 910 | Datacenter training | 32 AI Cores, 256 class AI TFLOPS | Atlas training systems | Launched in 2019 |
| Ascend 910B | Training and inference | CANN-compatible evolution | Domestic AI clusters | In production use |
| Ascend 910C | Training and inference | Higher-density system integration | 384-chip Atlas 900 A3 | Scaled in 2025 |
| Ascend 950PR | Prefill and recommendation | FP8 1 PFLOPS, FP4 2 PFLOPS, HiBL HBM | 950PR cards and SuperPoD | Planned for Q1 2026 |
| Ascend 950DT | Decode and training | 144 GB at 4 TB/s, 2 TB/s interconnect | 8,192-chip Atlas 950 | Planned for Q4 2026 |
| Ascend 960 | Train and serve | 2x 950 compute, memory, bandwidth, ports | 15,488-chip Atlas 960 | Planned for Q4 2027 |
| Ascend 970 | Train and serve | FP8 4 PFLOPS, FP4 8 PFLOPS target | Future SuperPoD | Planned for Q4 2028 |
The 950-and-later entries are Huawei's official 2025 roadmap, not verified shipment data. Unofficial estimates of the 910B and 910C process, memory and yield are deliberately excluded.
Ascend 310 and 910: the full-stack foundation
Ascend 310 covered cameras, edge servers and inference cards; Ascend 910 targeted datacenter training. Both used the Da Vinci AI core and the CANN software stack. Da Vinci combines cube, vector and scalar execution with memory-transfer engines. Explicit L0A, L0B, L0C, L1 and unified buffers make it a scratchpad architecture in which compiler and programmer control placement to reduce HBM traffic.
Published research describes 32 AI cores, a 16 by 16 by 16 tensor unit and approximately 34 MB of on-chip cache in Ascend 910, with a 256-class AI-FLOPS figure. Huawei system documents describe link capabilities at board and NPU levels under different conditions, so they should not be merged into a single peak claim.
CANN provides compiler, runtime, operator libraries, graph execution and Ascend C. Because the ISA and memory model differ from CUDA, adoption depends on porting and numerical validation, plus credible integration with PyTorch, PaddlePaddle, vLLM and other frameworks beyond Huawei's MindSpore tools.
Ascend 910B and 910C: deployment evidence over specification sheets
Huawei says it optimized 910B and 910C for DeepSeek inference demand in 2025. Ascend 910C is the building block of Atlas 900 A3. The company reported deliveries beginning in March 2025, with more than 300 SuperPoDs deployed to more than 20 customers. Each can contain as many as 384 chips linked through UnifiedBus 1.0; Huawei quotes up to 300 PFLOPS for the system. CloudMatrix384 exposes the hardware as a cloud service.
The valuable evidence is operational: hundreds of NPUs in one scale-up domain force firmware, link failures, topology, collectives, scheduling, cooling and checkpoints to mature together. Delivery volume does not independently prove sustained model performance, so public model throughput, effective utilization and recovery behavior matter more than unofficial equivalence claims against a GPU.
A roadmap that names the constraint
Huawei has said that mainland China may remain behind in advanced process technology. Its response is to connect more chips made on practically available nodes. This can improve supply and wafer yield, but multiplies memory stacks, packages, optics, power, cooling and software complexity.
N slower devices behave like one faster system only when collective communication and tail failures are controlled. An 8,192-device logical domain does not guarantee linear speedup. The strategy depends on effective UnifiedBus bandwidth, latency, fault isolation and compiler sharding.
Ascend 950: separating prefill and decode through memory
Ascend 950PR and 950DT use a common compute die with different proprietary HBM. Shared targets are 1 PFLOPS at FP8 or MXFP8/HiF8, 2 PFLOPS at MXFP4 and 2 TB/s of chip interconnect, which Huawei describes as 2.5 times 910C.
The core adds vector capability and combines SIMD with SIMT. Memory-access granularity falls from 512 to 128 bytes to improve fragmented and discontinuous access. That is a response to MoE routing, embeddings, attention and irregular vector work beyond dense tensors.
950PR is positioned for compute-heavy prefill and recommendation, using cost-oriented HiBL 1.0 memory. 950DT is positioned for bandwidth-heavy decode and training, with a proposed 144 GB at 4 TB/s using HiZQ 2.0. Splitting prefill and decode pools can better match compute-to-memory ratios, but activations and KV state must cross the pools. Disaggregation wins only if transfer and queueing cost is smaller than the utilization gain.
Atlas 950 and UnifiedBus 2.0
The planned Atlas 950 SuperPoD combines as many as 8,192 950DT devices, 160 cabinets and roughly 1,000 square meters. Huawei targets 8 EFLOPS at FP8, 16 EFLOPS at FP4 and 16 PB/s of aggregate interconnect in Q4 2026. An all-optical fabric joins 128 compute and 32 communication cabinets.
UnifiedBus 2.0 is described as a bus-grade protocol with peer coordination, resource pooling and high availability. Huawei quotes optical reach beyond 200 m, fault detection and protection switching near 100 ns, 2.1 microseconds of latency and TB/s-class bandwidth. UBoE extends the protocol over Ethernet.
The ambition is a scale-up domain spanning many racks and cabinets. Aggregate bandwidth hides link bandwidth, oversubscription, hop count and collective algorithms. Model-level tokens per second, job completion time and recovery behavior are more useful than the nominal device count. Huawei's projected training and inference multipliers versus Atlas 900 A3 lack sufficient public workload detail and should be treated as roadmap targets.
Ascend 960 and 970: what annual doubling requires
Ascend 960 targets twice the 950's compute, memory bandwidth, capacity and interconnect ports: 2 PFLOPS at FP8 and 4 PFLOPS at FP4. A 15,488-chip Atlas 960 is planned for Q4 2027. Ascend 970, planned for Q4 2028, targets 4 PFLOPS at FP8 and 8 PFLOPS at FP4, twice the interconnect and at least 1.5 times the memory bandwidth of 960. Huawei explicitly says the 970 specifications remain adjustable.
Annual doubling cannot come from process shrink alone. Lower precision, larger packages, more dice, more power and higher utilization all contribute. Changing the metric from FP16 to FP8 or FP4 inflates peak figures unless model quality and sustained utilization are demonstrated.
CANN's open strategy
Huawei announced plans to open the CANN compiler and virtual ISA interface for 910B and 910C and broaden access to the software stack. The goal is to monetize hardware while reducing adoption friction.
Source availability is not sufficient to replace CUDA. Documentation, compatibility, operator quality, profilers, governance and third-party kernels determine whether an ecosystem forms. China's deployment volume could close the gap if Ascend C, PyTorch adapters, vLLM and model libraries mature quickly.
Watch points
- Verified availability and customer deployment of 950PR.
- Volume and yield of the proposed 144 GB, 4 TB/s memory for 950DT.
- Sustained tokens per second, model FLOPS utilization and effective bandwidth on the 8,192-chip Atlas 950.
- Independent switch, optics and NIC participation in UnifiedBus 2.0.
- Whether CANN openness produces external contribution and compatibility, not only a source release.
Contrarian read
More NPUs may amplify the process disadvantage. Every added device requires memory, packaging, boards, optics, switches, power and coolant. Failure probability and stragglers rise, while all-to-all communication becomes more expensive. A nominally available domestic system could carry higher total capital and operating cost.
The thesis reverses if UnifiedBus delivers high effective bandwidth and fast recovery, and the domestic supply chain provides the required memory, optics and packages. Where the newest NVIDIA systems cannot be obtained reliably, usable domestic capacity can be economically superior despite lower per-chip efficiency.
Korean lens
Huawei's roadmap makes the strategic role of Korean HBM, packaging and optics unusually clear. A constrained compute node can still scale when memory and interconnect are available; without them, a compute die cannot become a SuperPoD. That opportunity is inseparable from export controls and geopolitical risk.
Korean NPU firms should report reliable-domain size, topology-aware compiler behavior and job recovery, not only TOPS. Separating measured workloads from vendor projections is essential to credibility.
Sources
- Huawei Ascend computing overview
- Atlas 900T logical architecture
- Ascend hardware architecture
- Ascend and SuperPoD roadmap keynote
- Huawei 2025 annual report
- Huawei CloudMatrix overview
Disclosure
This article is for informational purposes only and does not constitute a recommendation to buy or sell any security. Figures and facts are based on publicly available corporate disclosures, media reports and market research, and errors may occur in the source material or writing process. The author may hold shares of companies mentioned. Readers are solely responsible for all investment decisions and outcomes.
