d-Matrix at $2 Billion: Why the Market Pays for Compute Inside Memory

30-Second Summary

d-Matrix is valued at $2 billion because it sells the one thing inference economics is short of: memory bandwidth that does not leave the chip. The Santa Clara startup closed a $275 million Series C on November 12, 2025 at a $2 billion valuation (about 2.8 trillion won at 1,400 won per dollar), bringing total funding to $450 million. Its Corsair accelerator computes inside SRAM — Digital In-Memory Computing, or DIMC — and claims 150 TB/s of on-chip bandwidth per card, up to 30,000 tokens per second on Llama 70B at 2 ms per token, and 3–5x better energy efficiency than GPU-based systems. Corsair entered full production in June 2026. The $2 billion price is not payment for today's revenue. It is payment for an option: that when inference becomes the dominant AI cost, the winning architecture is the one that treats memory, not arithmetic, as the product.

Background: A Company Built for the Second Half of AI

d-Matrix was founded in 2019 in Santa Clara, California, by Sid Sheth (CEO) and Sudeep Bhoja (CTO). The founding bet was unfashionable at the time: training would not remain AI's binding constraint. Once models are trained, they must answer questions continuously, at scale, for paying users — and that serving phase, inference, would become the industry's dominant cost. The company spent six years building for that phase before the market agreed with it.

The funding history tracks the thesis gaining believers. A $110 million round in 2023 brought in Microsoft's venture fund M12. The Series C in November 2025 was co-led by BullhoundCapital, Triatomic Capital and Temasek, with new participation from the Qatar Investment Authority (QIA) and Singapore's EDBI, and follow-on capital from M12, Nautilus Venture Partners, Industry Ventures and Mirae Asset. Total raised reached $450 million, and headcount passed 250 across Santa Clara, Toronto, Sydney, Bangalore and Belgrade.

The timing matters. By late 2025, hyperscalers were publicly shifting capital expenditure from training clusters toward inference fleets, and the industry's center of gravity moved from "how fast can we train" to "what does each token cost." d-Matrix is one of the few startups that designed its silicon from day one for the second question. That is the background against which a $2 billion valuation for a pre-scale chip company has to be read.

Business Deep Dive

The product: compute where the weights live

Decode-phase inference is memory-bound. Generating each token requires reading the model's weights, and a GPU spends much of its time and energy moving those weights between HBM stacks and compute units. Corsair attacks the movement itself. Its DIMC cores perform matrix operations inside SRAM arrays, so the weights are computed on where they sit instead of being fetched to where computation happens.

The shipping card's numbers define the trade. Each Corsair card, built on TSMC's 6 nm process in a standard PCIe Gen5 form factor, delivers 2,400 TFLOPS of peak 8-bit compute, 2 GB of on-chip Performance Memory (SRAM) running at 150 TB/s, and up to 256 GB of off-chip LPDDR5 Capacity Memory. Compare the bandwidth figure with HBM: a leading HBM3e stack delivers roughly 1.2 TB/s per stack, and even a full GPU package aggregates on the order of 8 TB/s. Corsair's 150 TB/s is on-chip SRAM bandwidth, not package bandwidth — a different quantity, and the comparison flatters d-Matrix. But the direction is real: for small-batch, latency-sensitive decode, keeping weights in SRAM removes the round trip that dominates GPU token latency.

The platform around the chip is what the Series C money actually buys. JetStream NICs connect cards and racks at low latency. The Aviator software stack compiles models from PyTorch and Triton onto the DIMC fabric. SquadRack, a reference rack architecture built with Arista, Broadcom and Supermicro, packages the cards into deployable systems, and Squadron clusters, announced as generally available in October 2026, scale to 1,024 Corsair XPUs across 16 racks in standard air-cooled data centers. In June 2026 Corsair entered full production, with volume shipments directed at hyperscalers, neoclouds and frontier AI labs. In April 2026 the company also acquired GigaIO's data center business, adding the FabreX memory fabric and SuperNODE system designs.

The SRAM ceiling, and why Raptor exists

The architecture's strength is also its ceiling. SRAM is fast and ruinously expensive per bit. Corsair's 2 GB of Performance Memory cannot hold a 70B model; the rest lives in LPDDR5 Capacity Memory, and the system's real performance depends on how cleverly Aviator tiles work between the two tiers. SRAM also does not shrink like logic: at advanced nodes its density improves slowly, so a pure-SRAM roadmap gets more expensive per token-generating capacity every generation, not less. This is the process-economics question every in-memory computing startup must answer.

d-Matrix's answer is 3DIMC, embodied in the next-generation Raptor platform. Announced through the Pavehawk test vehicle with Alchip in November 2025, Raptor bonds a TSMC 4 nm logic die face-to-face onto a custom DRAM die at a 36-micron pitch. The company projects more than 100 TB/s of bandwidth and 32 GB — 256 Gb — of stacked memory per accelerator at 0.37 pJ/bit, and early silicon results presented in 2026 reported roughly 4.7x higher inference throughput per accelerator than an HBM-based configuration. Raptor is scheduled to tape out by the end of 2026, with rack availability in the fourth quarter of 2027. In September 2026 d-Matrix joined NVIDIA's NVLink Fusion ecosystem, so Raptor XPUs are designed to plug into NVIDIA MGX racks alongside GPUs rather than demanding a forklift replacement.

What must be true for $2 billion

Strip the story down to arithmetic. A $2 billion valuation on $450 million raised, before volume revenue, prices d-Matrix as a future platform business, not a component vendor. Three things must hold. First, inference spending must keep compounding so that a specialized decode layer is a budget line hyperscalers fund separately from GPUs. Second, Corsair's claimed economics — 10x interactivity, 3x better performance per total cost of ownership, 3–5x energy efficiency, all company-reported figures — must survive contact with production workloads at named customers, not just Llama benchmarks. Third, the software moat must form: Aviator has to become sticky enough that customers do not treat the hardware as a swappable commodity when NVIDIA, AMD or a hyperscaler's own ASIC team ships a good-enough answer.

The traction evidence so far is real but incomplete. Full production status, a Supermicro-built rack line, an acquisition that adds system-level fabric, and a sovereign-wealth-heavy investor roster (Temasek, QIA, EDBI) all signal that sophisticated buyers are doing diligence and staying. What is still missing is the evidence class that ultimately prices chip startups: disclosed production deployments with named hyperscalers and repeat orders. A reported July 2026 effort to raise further capital at a higher valuation, and reported NVIDIA interest in investing, remain unconfirmed and should be treated as reported, not established.

The downside: HBM fights back, and software is the tax

The bear case has two prongs. The first is physics and roadmaps. HBM is not standing still: HBM4 widens the interface to 2,048 bits per stack, and GPU vendors are integrating larger SRAM, faster interconnects and inference-optimized SKUs of their own. Every generation narrows the latency gap that justifies a separate accelerator, while the GPU incumbent offers one software stack for training and inference alike. The second prong is the adoption tax. Every non-CUDA platform asks customers to port models, trust a young compiler, and accept vendor risk on a startup's balance sheet. d-Matrix mitigates this with heterogeneous positioning — Corsair as a decode offload beside GPUs, formalized by the NVLink Fusion move and the Attention-FFN Disaggregation (AFD) demonstration, which split attention onto GPUs and feed-forward layers onto Corsair XPUs and showed 845 tokens per second per user across 64 concurrent users. Mitigation is not elimination: the tax is paid in every sales cycle.

Chase's Take

Most AI chip startups are selling a faster engine. d-Matrix is selling a different accounting identity: in decode inference, tokens per second is roughly bandwidth divided by model size, so the company that owns the bandwidth owns the margin. Choosing digital over analog in-memory compute was the quietly correct decision — analog IMC demos beautifully and calibrates terribly, while DIMC keeps SRAM's determinism and survives process migration. The honest question is not whether the physics works; Pavehawk and the 2026 silicon results say it does. The question is whether SRAM economics plus a young software stack can hold a defensible layer against an incumbent that can bundle its answer into the GPU rack the customer already bought. The NVLink Fusion decision tells me management understands this: d-Matrix is not trying to beat NVIDIA's rack, it is trying to become a line item inside it. At $2 billion, investors are not paying for that outcome — they are paying for the probability-weighted path to it, with Series C cash funding exactly the two proofs still missing: named production scale and Raptor on schedule.

Implications

For hyperscalers and neoclouds: Corsair-class accelerators turn inference into a heterogeneous design problem. The procurement question shifts from "which GPU" to "which layers run where," and AFD-style disaggregation becomes a capacity-planning discipline, not an experiment.

For the memory industry: d-Matrix is a demand signal with a warning attached. Its current product routes around HBM with SRAM and LPDDR5, and Raptor's custom stacked DRAM suggests the long-term contest is not HBM versus nothing — it is standard HBM versus memory designed around a specific compute die. Memory makers that co-design stacks with accelerator startups gain a channel the GPU duopoly does not control.

For investors: The $2 billion mark will be re-priced by two observable events: the first named, repeat hyperscale deployment of Corsair, and Raptor's tape-out by the end of 2026. Until then, the valuation rests on benchmark claims and investor quality — strong signals, but signals, not cash flow.

FAQ

What does d-Matrix do?

d-Matrix builds data-center accelerators specialized for AI inference. Its Corsair platform uses Digital In-Memory Computing (DIMC) — performing computation inside SRAM — together with JetStream networking and the Aviator software stack, targeting low-latency, energy-efficient token generation rather than model training.

Why is d-Matrix valued at $2 billion?

The $2 billion valuation was set by its $275 million Series C closed on November 12, 2025, co-led by BullhoundCapital, Triatomic Capital and Temasek, with participation from QIA, EDBI and Microsoft's M12. Investors are pricing the expectation that inference becomes the dominant AI infrastructure cost and that a memory-centric architecture captures a durable share of it.

How is Corsair different from a GPU?

A GPU reads model weights from HBM for every token, at package bandwidth on the order of 8 TB/s. Corsair keeps hot weights in on-chip SRAM and computes inside the memory array, reaching 150 TB/s of on-chip bandwidth per card, which targets the small-batch, low-latency decode workloads where GPUs are least efficient. Corsair carries 2 GB of SRAM Performance Memory plus up to 256 GB of LPDDR5 Capacity Memory per card.

What is 3DIMC and Raptor?

3DIMC is d-Matrix's 3D-stacked evolution of its in-memory architecture. The Raptor platform bonds a 4 nm logic die face-to-face onto a custom DRAM die, projecting over 100 TB/s of bandwidth and 32 GB (256 Gb) of memory per accelerator. Raptor is scheduled to tape out by the end of 2026, with rack availability planned for the fourth quarter of 2027, including integration into NVIDIA NVLink Fusion racks.

Note: Performance and efficiency figures (10x interactivity, 3x performance per TCO, 3–5x energy efficiency, 150 TB/s) are company-reported as of the dates cited in the text. The $2 billion valuation is the reported post-money figure from the November 2025 Series C announcement. Won conversions use 1 dollar = 1,400 won.

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