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DeepX Plugs Its NPU Into Intel's Software: The Ecosystem Bet of a Korean AI Chip Startup

DeepX is integrating its DX-M1 NPU into Intel's OpenVINO as a selectable processor, with initial results due early next year. Talks with AMD are open but still at the direction-setting stage. The structural read: for edge NPUs, the gate is software ecosystem friction, not TOPS.

DeepX Plugs Its NPU Into Intel's Software: The Ecosystem Bet of a Korean AI Chip Startup
Illuminated microchip on a complex electronic circuit board
Photo by Brecht Corbeel on Unsplash

30-Second Summary

DeepX, a South Korean fabless startup that designs low-power neural processing units (NPUs), is integrating its DX-M1 chip into Intel's OpenVINO software toolkit as a selectable inference processor, CEO Kim Nok-won said in an interview on October 15, 2026. Initial results are expected early next year, with a formal partnership announcement to follow. The company has also opened working-level talks with AMD after an October 7 roundtable in Seoul with AMD CEO Lisa Su, though both sides describe the discussions as direction-setting rather than a concluded partnership. At the same time, DeepX's next-generation chip, the DX-M2 built on Samsung Foundry's 2nm process, tapes out this month, with first silicon due in March–April 2027. The common thread is strategic: DeepX is betting that for edge AI chips, the decisive battleground is not raw TOPS but how little friction a chip creates inside other companies' software stacks and distribution channels.

Background

DeepX was founded in 2018 by Kim Nok-won, who holds a Ph.D. in electrical engineering from UCLA and previously worked at Broadcom, Cisco, and IBM. The company is a fabless designer: it develops AI inference chips and outsources manufacturing. Its products target on-device and edge AI — robots, drones, industrial PCs, smart cameras, and smart glasses — where devices must run AI models locally, at a few watts, without a cloud connection.

The flagship product, DX-M1, entered mass production in August 2025 on Samsung Foundry's 5nm process. It delivers up to 25 TOPS of AI compute at 3–5W, ships as an M.2 module that slots into existing systems, and is priced under $100 per chip, according to the company. DeepX reports a mass-production yield of 91.1% for the chip — a company-disclosed figure, but one that matters because it underwrites the low price.

The commercial traction is measurable. Between August 2025 and July 2026, DeepX booked 77 purchase orders from customers in more than 10 countries, worth a cumulative ₩18.3 billion (about $13 million). Roughly 300 companies worldwide — more than 100 of them in Korea — are evaluating its chips, and the company has signed 27 distribution agreements, with offices planned in Japan and Europe. Reported revenue rose from ₩3.3 billion in 2025 to more than ₩20 billion in 2026. Disclosed customers and platform partners include Hyundai Motor Group's robotics business, industrial computing leaders Advantech and AAEON, Lenovo, and Baidu.

Funding has followed the traction. DeepX raised ₩110 billion in a Series C in May 2024, and a Series D is under way in 2026; in October, Samsung Securities and SVIC 33, a partnership managed by Samsung Venture Investment, subscribed to a US$12.3 million allotment of new shares.

Business Deep Dive

What the OpenVINO integration actually changes

OpenVINO is Intel's open-source toolkit for deploying AI inference across CPUs, GPUs, and accelerators. Developers write to its APIs and model format once, then choose the hardware device at runtime. DeepX is adding its NPU as one of those selectable devices, and is doing the model-optimization and developer-tool work to make that path production-grade.

The practical significance is best understood from where DeepX chips already sit. DeepX NPUs are already designed into industrial PCs built on Intel processors — but today, the integrator has to install and wire up DeepX's software manually. Every manual step is a tax on adoption: engineering hours for the OEM, a support burden for DeepX, and a reason for a design to stay in "evaluation" instead of moving to production. Becoming a native OpenVINO device removes that tax. A developer already using OpenVINO — the default inference stack across much of the Intel-based industrial PC world — can target DeepX silicon by changing a device string, not by adopting a new SDK.

This is why the sequence matters. DeepX says it will announce the Intel partnership formally only after the integration produces results, with initial results expected early next year. That is a results-first posture, and it signals the integration is engineering work in progress, not a memorandum.

Diagram of a DeepX NPU connected to the OpenVINO toolkit and other software platforms
The DeepX NPU as a selectable device inside the OpenVINO ecosystem. Source: VLSI Korea

What Intel gets out of it

OpenVINO's strategic value to Intel rises with every accelerator it supports. Intel's own silicon roadmap does not directly address the sub-5W discrete add-in accelerator niche: as Kim noted at the AMD roundtable, NPUs integrated into CPUs reach 40–50 TOPS but rarely in 5W-class parts, so robots and field devices need a low-power companion accelerator sitting next to the CPU. If OpenVINO becomes the layer through which those companion chips are programmed — including chips Intel does not make — Intel keeps the software standard even where it does not win the silicon. For DeepX, the equation is symmetrical: it borrows Intel's installed base and developer habits instead of building a proprietary stack from zero, which is precisely the fight a startup with finite software headcount cannot afford to lose slowly.

The AMD talks: real substance, clear limits

The AMD storyline needs careful calibration. The October 7 event in Seoul was a roundtable hosted around a Korean government–AMD memorandum signed in July; 13 Korean AI infrastructure companies — including FuriosaAI, Rebellions, and Mobilint — sat with Lisa Su. The agenda was structural: heterogeneous computing that combines AMD CPUs and GPUs with Korean NPUs, participation in AMD's open ROCm software ecosystem, and reference designs the government wants to validate domestically and export. AMD committed to opening an AI research center in Korea within the year.

Within that frame, DeepX's bilateral follow-up is genuine but early. Kim said he confirmed AMD's willingness to work with outside companies on an open physical-AI ecosystem; AMD's technical team followed up by email; and DeepX planned to meet AMD's Korea head the following week to discuss specifics. Kim himself characterizes the stage as confirming direction through working-level talks. There is no announced technical collaboration, no joint product, and no ROCm integration commitment for DeepX silicon.

Two facts keep the story grounded. First, coexistence at the channel level already exists: products combining AMD systems with DeepX NPUs are already on the market through distributor Avnet. Second, the structural logic is real — AMD's open-ecosystem strategy needs non-AMD accelerators to plug into its CPUs and GPUs, and Korean NPUs need a global platform's distribution gravity. What exists today is an opened door with a government holding it, not a signed alliance.

Edge devices — industrial PC, robot, drone, smart camera and smart glasses — using a low-power NPU
Where edge NPUs ship: industrial PCs, robots, drones, smart cameras and smart glasses. Source: VLSI Korea

The Korean NPU map: two different games

Korea's NPU startups are often lumped together, but they are playing different sports. Rebellions and FuriosaAI target data-center inference: FuriosaAI's RNGD is a 180W PCIe accelerator for servers, and both companies sell performance per watt at rack scale to cloud and enterprise buyers, against Nvidia's ecosystem gravity. DeepX and Mobilint target the edge: watts in the single digits, prices under $100, and buyers who are device OEMs and industrial PC makers rather than data-center operators.

The moat logic differs accordingly. Data-center players must survive a software war — compiler maturity against CUDA. Edge players must survive a distribution war: shelf space in Advantech and AAEON platforms, distributor agreements across 27 partners, compatibility with the toolchains integrators already use. DeepX's recent moves are all distribution-and-toolchain moves. It has completed software work with Amazon Web Services so models trained in the cloud can be deployed onto DeepX devices, and it plans robot software compatible with Nvidia's Isaac platform within the year. OpenVINO, AWS pipelines, Isaac compatibility — none of these is a silicon announcement. All of them reduce the number of reasons an integrator can say no.

The silicon roadmap runs in parallel, as the second front. The DX-M2, on Samsung Foundry's 2nm process, tapes out in October 2026, with first chips expected in March–April 2027 and mass production targeted later in 2027; the company targets up to 80 TOPS in the same low-power class. DeepX is also a flagship Korean fabless on Samsung's leading-edge nodes while most peers manufacture at TSMC — a positioning that aligns it with Korea's sovereign-AI policy push, and one that lives or dies on Samsung 2nm execution. Kim has publicly expressed confidence that 2nm yields can start in the low-70% range and climb above 80% within a year; the claim will be tested by the DX-M2 ramp.

Chase's Take

The edge AI market will not be won by the best chip. It will be won by the chip that costs an integrator the fewest engineering hours. DeepX's management clearly understands what it actually sells: not a processor, but a line item in someone else's bill of materials. The buyer at Advantech, AAEON, or Lenovo does not ask "how many TOPS?" first. They ask "how much work to ship this in my box, and who supports it?" Every DeepX announcement this year — OpenVINO integration, AWS deployment pipeline, Isaac-compatible robot software, 27 distributors — is an answer to that second question.

That framing also prices the AMD talks correctly. They are an option, not an asset: valuable because AMD's open-ecosystem push is real and government-backed, worthless until a technical scope exists. The OpenVINO work is the opposite — unglamorous, specific, and aimed at the exact point of friction in DeepX's existing Intel-based design wins. If I had to rank what moves DeepX's 2027 revenue, it is OpenVINO shipping on schedule, DX-M2 sampling on time, and the ~300 evaluating companies converting into purchase orders — in that order. The IPO, which Kim says he would like to pursue within three years at the latest, is a milestone that follows those three, not a substitute for them.

Implications

  • For device OEMs and integrators: a sub-5W, sub-$100 inference option that targets the software stacks already in use — OpenVINO for Intel-based industrial PCs, AWS for cloud-trained model deployment — lowers the switching cost of trying a non-Nvidia accelerator at the edge.
  • For Korea's AI chip policy: the sovereign-AI program is producing distribution tailwinds, not just subsidies. The AMD roundtable format — platform holder, government convener, local startups — is a template other platform companies will be measured against.
  • For edge NPU competitors: shelf space is the contest. Global edge rivals compete for the same OpenVINO device list, the same industrial PC platforms, and the same distributors. Toolchain presence is becoming a prerequisite, not a differentiator.
  • For investors: the question shifts from "can the chip win designs?" — 77 purchase orders say it can — to "can design wins compound into platform lock-in before the 2nm generation resets the race?" Series D execution and the early-2027 OpenVINO results are the next two checkpoints.
Platform / partnerWhat is happeningStatus / timing
OpenVINO (Intel)DX-M1 added as a selectable inference device in OpenVINOInitial results expected early next year; formal partnership announcement to follow
AMDWorking-level talks after the October 7 Seoul roundtable with CEO Lisa SuDirection-setting only; no announced technical collaboration and no ROCm integration commitment
AWSSoftware work so models trained in the cloud can be deployed on DeepX devicesCompleted
NVIDIA IsaacRobot software compatible with the Isaac platformPlanned within the year
DX-M2 (Samsung Foundry 2nm)Next-generation chip targeting up to 80 TOPSTape-out in October 2026; first silicon in March–April 2027

FAQ

Q: What exactly is DeepX integrating into Intel's OpenVINO? A: DeepX is adding its NPU as a selectable inference processor inside OpenVINO, Intel's deployment toolkit, together with model optimization and developer-tool support. Initial results are expected early next year, and the company plans a formal partnership announcement after those results are in. Today, using DeepX chips in Intel-based industrial PCs requires manually installing and connecting DeepX's software.

Q: Is DeepX partnering with AMD? A: Not yet. After the October 7, 2026 roundtable in Seoul with AMD CEO Lisa Su, the two sides opened working-level talks and AMD's technical team followed up by email. CEO Kim Nok-won describes the stage as confirming direction. No technical collaboration or joint product has been announced — although products combining AMD systems with DeepX NPUs already sell through distributor Avnet.

Q: What are the specs of the DX-M1 and the upcoming DX-M2? A: The DX-M1 is built on Samsung Foundry's 5nm process, delivers up to 25 TOPS at 3–5W, and has been in mass production since August 2025. The DX-M2 uses Samsung's 2nm process, tapes out in October 2026, with first chips expected in March–April 2027 and mass production targeted later in 2027; DeepX targets up to 80 TOPS in a similar low-power envelope.

Q: When will DeepX go public? A: No date has been set. Kim has said he would like to complete an IPO within three years at the latest, describing it as a tool and a milestone toward becoming a global industry leader. The company has previously indicated it would consider a domestic Korean listing first.

Note: Order, revenue, and yield figures cited above are company disclosures made in interviews and briefings and have not been independently audited.

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