No Design Openings? Why Verification or PD Is the Wrong Detour

30-Second Summary

• Verification headcount has overtaken design. Per the Wilson Research Group Functional Verification Study (2022), the CAGR of mean peak engineers per project from 2007 to 2022 was 6.2% for verification vs 2.7% for design. The average ratio is about 1:1, reaching 5:1 (verification to design) in processors.
• Korea's hiring market is hot — with a catch. Large-company semiconductor postings in Q3 2026 rose 102% year over year (JobKorea data). But experienced-hire postings jumped 157% while new-grad postings grew only 55% — the door for juniors is narrower than it looks.
• The detour becomes permanent. A verification engineer who can't read RTL intent verifies what they can't design; a PD engineer who can't read RTL implements what they can't read. Your last title follows you into every future interview.
• Salary facts (Korea). Average base salary for semiconductor engineers is about KRW 82.96M: KRW 58.5M for 1-3 years of experience, KRW 95.6M for 8+ years (ERI SalaryExpert, 2026). Reported new-grad base: about KRW 54M at SK hynix, KRW 48-53M at DB HiTek.
• The answer is the order. Learn RTL first, then verification, synthesis, PD, and STA/signoff. Even if you enter through verification or PD, start with RTL and keep moving forward — never sideways.

Intro: the question I get asked most

Of all the reader questions I receive, this one comes up most often:

"I want to do RTL design, but there are no design openings. Can I join verification or PD first and move to design later?"

Let me be direct: that detour usually becomes permanent. People who enter through verification stay verification engineers; people who enter through PD stay PD engineers. Not because they lack willpower — because the structure works that way.

This article shows that structure with data, then gives the answer for anyone already walking that road: the order. Learn front-to-back.

Deep Dive

Episode 1. What the hiring market actually says: yes, verification has more seats

Facts first. It is true that verification has more openings — overwhelmingly so.

According to the Wilson Research Group Functional Verification Study (2022), the compound annual growth rate of mean peak engineers per IC/ASIC project between 2007 and 2022 was 2.7% for design engineers and 6.2% for verification engineers. Verification headcount grew 2.3x faster than design. Today the average project runs at roughly a 1:1 verification-to-design ratio, and in processor segments it stretches to 5:1. (Source)

The 2020 edition adds a sharper number: design engineers spend 47% of their time on verification-related work. You cannot escape verification even as a designer. That sounds like an argument for the detour, but it is the opposite — it is an argument that designers must know verification. (Source)

Korea's market is hot too. JobKorea's data shows large-company semiconductor and display postings in Q3 2026 rose 102% year over year, with semiconductor engineer postings up 55% cumulatively through Q3. (Source)

But read one more line: experienced-hire postings surged 157% while new-grad postings grew only 55%. With AI memory demand rising, companies are weighting hires they can deploy immediately. Posting counts are up, but the door for new graduates is narrower than the headline suggests. The "just get in through verification" strategy only works if that door is actually open to juniors.

One honest disclosure. This article does not present exact posting counts for RTL design vs verification vs PD. Korean job platforms (Saramin, JobKorea) do not publish role-level aggregates, and there was no way to verify them via text fetch. The numbers above rest on verifiable data: project staffing structure (Wilson) and overall hiring trends (JobKorea). Anyone needing role-level posting counts should ask the platforms directly or consult a paid report.

Episode 2. Why the detour becomes permanent

More seats does not mean the detour is safe. Three mechanisms make it permanent.

First, verification is the act of reading RTL intent.

You can learn to write a UVM testbench. The problem is what comes after. If you cannot read RTL intent — why the designer wrote the code this way — you end up confirming that things "look like they work" instead of finding bugs. You can hit 100% coverage and still miss every bug born from misreading the spec. It is no accident that the Wilson 2020 study found roughly two-thirds of ASIC/IC projects experiencing at least one respin: verification headcount keeps growing, but headcount does not buy verification quality.

Second, PD without the "why" leaves you a tool operator.

You can run CTS, do routing, and push timing ECOs. But if you don't know why this pipeline stage sits here, or why this structure is timing-friendly, you cannot make PPA (power, performance, area) tradeoff decisions. The gap between someone who runs what they're told and someone who understands the structure becomes brutal from year three onward.

To put it plainly: a verification engineer who doesn't know RTL verifies what they can't design, and a PD engineer who can't read RTL implements what they can't read. Both can produce "something that works." Neither knows why it works. And an engineer who doesn't know why cannot produce an answer when a hard problem arrives.

Third, the inertia of titles.

The hiring market calls you by your last title. A verification engineer with three years of experience who applies for a design role gets asked: "Why do you want to leave verification?" And then competes against designers with three years of RTL experience — while reading RTL worse than they do. The switch that was easy in year one gets sharply harder from year three. The detour is wide on entry and narrow on exit.

Episode 3. Salary facts: leverage pays, not titles

"So which pays more — verification or PD?" Data again.

Per ERI SalaryExpert (2026), the average base salary for semiconductor engineers in South Korea is about KRW 82.96M — KRW 58.5M for 1-3 years of experience and KRW 95.6M for 8+ years. (Source) Reported new-grad base salaries run about KRW 54M at SK hynix and KRW 48-53M at DB HiTek. (Source 1, Source 2)

And the second honest disclosure: I could not find published salary bands split by role (RTL design vs verification vs PD) for Korea. The ERI figures are role-blended, and within the same job grade at large Korean companies, starting pay differs little across design, verification, and PD — they share the same grade system and bonus tables.

So what actually differentiates pay? Not the title — leverage. The expensive engineers are the verification engineer who reads RTL, the PD engineer who understands architecture, the STA engineer who reads the intent of every upstream stage and signs off. STA/signoff engineers command a premium for exactly this reason: signoff is the seat where you must read the intent of the entire flow, which is impossible without the front end. The pay gap at year five comes not from which title you hold but from how much of the flow you can read.

Episode 4. The answer is the order: the front-to-back rule

That was the diagnosis. Here is the prescription, and it is simple: learn in order. RTL first.

Learning in the order chips get built — front-to-back — is the fastest path. Here is what to hold in your hands at each stage:

1. RTL Design — Verilog/SystemVerilog, FSMs, pipeline structures, CDC basics. Writing synthesizable RTL yourself. Without this, every later stage is a black box.
2. Verification — UVM testbench structure, SVA (assertions), functional coverage closure, the concept of formal. After writing RTL, you learn how to prove what you built.
3. Synthesis — constraints (SDC basics), lint, and how a netlist differs from RTL.
4. Physical Design — floorplan, power plan, CTS, routing, and the concept of physical verification (DRC/LVS).
5. STA / Signoff — writing timing constraints, timing exceptions, timing closure, signoff criteria.

There is also a realistic plan for those already working in verification or PD: one hour a day outside work, six months. Write a small IP — a UART or SPI — in Verilog yourself, run synthesis, run STA on it. Start from building, not reading. Only people who have built something can read intent.

One line to compress it all: don't move sideways — move forward. Drifting sideways from verification to PD to DFT is not movement; it is drift. Only moving forward along the flow, starting from RTL, becomes a career.

Learning roadmap via edu.vlsi.kr

This article's "learn in order" thesis points the same direction as VLSI Edu's RTL2GDS roadmap. That page's career horizon section maps where learned skills lead next — design, verification, EDA, foundry, and equipment companies' global careers (Samsung, SK hynix, NVIDIA, Qualcomm, AMD, Arm, Intel, Broadcom, Marvell, Micron, TSMC, Cadence, Synopsys, ASML). I opened and verified this page directly.

The third honest disclosure: the deeper roadmap and tutorial pages could not be opened via text fetch (it's a JavaScript-rendered site), so I could not verify their URLs. The topics below connect directly to this article's order — if these pages exist on VLSI Edu (or when they do), following them in this sequence is the playbook:

1. RTL design roadmap — Verilog/SystemVerilog basics → synthesizable RTL coding → AMBA protocols (AXI/AHB) → designing a small IP yourself. Stage 1 of Episode 4.
2. Verification roadmap — UVM testbench structure → SVA → functional coverage closure → the concept of formal verification. Stage 2.
3. STA/signoff roadmap — writing SDC → timing exceptions → timing closure → signoff criteria. Stage 5, and the segment with the highest salary leverage.
4. PD roadmap — floorplan → power plan → CTS → routing → physical verification. Stage 4.

Chase's Take

I am a Staff Product Engineer at Synopsys building PrimeTime, PrimeShield, and PrimePower. STA and signoff tools are my day job — I stand, professionally speaking, at the very end of the back end.

But before that, I owned full RTL-to-GDS at SiFive Korea: Samsung nodes from 5nm to 14nm, more than five tapeouts, including the physical implementation of chips like Rebellions ATOM, FuriosaAI WARBOY, and RHEA, from start to finish.

There is a reason someone who builds back-end tools tells juniors to learn the front end first. When you hit a timing violation in STA, the place you end up is always RTL intent. Writing SDC, judging an ECO — without the front end, it becomes a fight against "numbers the tool spit out." You can read the numbers without knowing why they came out. The user I fear most while building PrimeTime is exactly that user: one who trusts the tool and never suspects the RTL.

So I say this: you have to touch the whole flow. An engineer who has handled the entire flow with their own hands and an engineer who knows one segment become completely different people after five years. Don't regret starting in verification or PD. Just don't stop there. Learn RTL and move forward. The order is the answer.

FAQ

Q1. If I start in verification, can I really never move to design?
It's not that you can't — it's that the cost of moving grows every year. In year one it isn't hard. But by year three you're competing against designers with three years of RTL experience, and interviews ask why you want to leave verification. That's why you should learn RTL now, not "later."

Q2. Does PD pay less than design?
Within the same job grade at large Korean companies, starting pay differs little across design, verification, and PD — and there is no published role-split salary band data (see Episode 3). The gap opens up after about five years, and it comes from leverage — how much of the flow you can read — not from the title.

Q3. Verification has more openings — can't I just target verification?
Verification itself is an excellent career. The problem is taking verification as a detour when you want design. If verification is the goal, aim for its peak — formal verification, UVM architecture, verification leadership. A detour is dangerous when it's a compromise, not a goal.

Q4. I'm already working in verification/PD. How do I start RTL?
One hour a day outside work is enough. Write a small IP — a UART or SPI — in Verilog yourself, run synthesis, run STA on it. Don't just read; build. Only people who have built something can read intent. Follow the RTL design roadmap order in the edu.vlsi.kr section above.

This article is general career information, not investment or immigration advice.