Where Should a New Grad Go: Design vs Verification vs PD

30-Second Summary

• The widest-open door is verification (DV). On average, 55% of IC/ASIC project time goes to verification (Wilson Research Group, via Siemens EDA). While design headcount stood still, verification headcount grew at 6.8% CAGR from 2007 to 2020.
• Starting pay barely differs across the three tracks. In Korea: Samsung DS ~KRW 55M base, SK hynix ~KRW 54M base (community-compiled, 2026). What separates first-year total comp is the employer's bonus structure, not the job title.
• The real competition is the gate, not the track. Samsung's 2026 fall hiring is expected at ~10,000 group-wide, with ~4,500 absorbed by the DS division (Maeil Business Newspaper). GSAT test-takers alone are projected at 80,000–100,000 — the filter comes before the track choice.
• Five years out, the tracks diverge at the skill ceiling. RTL design leads toward architect, verification toward methodology/formal leadership, PD toward timing-closure and implementation lead. U.S. employer-disclosed ranges (Apple, Synopsys) show all three tracks reaching mid-200Ks base at senior levels.
• The thesis: entry is luck, but learning order is a choice. Entered through DV? Write RTL on the side. Entered through PD? Read RTL. Whichever door you walk through, keep the front-to-back order alive.

Intro: An Honest Answer to "What Should I Do?"

The most common question from soon-to-be graduates: "Design, verification, or PD — which one?" The honest answer is simpler than you'd like. Right now, any of them — walk through the door that's open. And after you enter, respect the order.

That may sound cold. But the numbers explain it. More than half of the time spent building a chip goes to verification. Yet students fixate on the word "design." Plenty want to do RTL design; few realize how short the industry is on people who break designs and prove them correct. The gap between demand and supply — that's where this article starts.

This is a side-by-side comparison of the three tracks: hiring volumes, competition, starting pay, skill ceilings, five-year career arcs, and work-life reality. Korea-first, with verifiable numbers cited with sources. And at the end, a playbook that works no matter which door you entered. This is the fifth piece in the "learn from the front" series.

Deep Dive: Five Episodes

Episode 1. Hiring Volume — Verification's Door Is the Widest

Numbers first. The Wilson Research Group IC/ASIC Functional Verification Trend Report (sponsored by Siemens EDA, the industry's standard survey) finds that verification consumed 55% of total project time in 2016 and 53% in 2018 — over half, for more than a decade. Design engineers themselves spend 47% of their own time on verification (2020 data). And the headcount trend is decisive: between 2007 and 2020, demand for IC/ASIC design engineers grew at ~3% CAGR, while demand for verification engineers grew at 6.8% CAGR — more than twice as fast.

How does that translate into job postings? A typical chip team staffs roughly two verification engineers per RTL designer. The industry needs more people who break and prove designs than people who write them. The 2024 survey recorded a first-silicon success rate of just 14% — the lowest in two decades — which only raises the price of verification.

What about Korea? Samsung's 2026 fall hiring round is the telling example. Up to ~10,000 new hires are expected across 20 Samsung affiliates, with nearly half — ~4,500 — expected to be absorbed by Samsung Electronics' DS division (Maeil Business Newspaper, October 2026). Inside DS, design, verification, PD, and process roles mix, but structurally the verification and PD (implementation) headcount is wider than design. Design is a small elite team; verification and PD are fought with volume — standard wisdom in the fabless and design-services world.

Design services tell the same story. Harman Connected Services (HCS) Korea runs ~230 people doing verification and PI/PD for Samsung SoC projects — AP, automotive, modem (per their official postings). Korean design houses like SEMIFIVE, ADTechnology, and Gaonchips keep hiring verification and PD engineers as tapeout volume grows. For a new grad, the realistic on-ramp into the chip industry is closer to this side than you'd think.

Bottom line: by headcount, it's DV > PD > RTL design. Wanting "design" is understandable, but the market opens its widest door on the verification side. That's a fact.

Episode 2. Salary Comparison — The Gap Is Smaller Than You Think

In Korea (2026), starting pay across the three tracks barely differs. At the big two (Samsung DS, SK hynix), new-grad base is ~KRW 54–55M: Samsung DS ~55M, SK hynix ~54M, foreign R&D centers like Micron Korea also ~54M in community compilations (Naver job communities and blogs — not official company figures).

What matters isn't base but first-year total comp. Community compilations put Samsung DS new-grad first-year total at KRW 85–95M and SK hynix at KRW 110–150M (yeon0720.tistory.com, 2026 roundup). The gap comes from bonus structure, not job title: Samsung's OPI is capped at 50% of annual salary, while SK hynix removed the PS cap entirely in a September 2025 labor agreement. Same "verification engineer" title — the company you join matters more than the track you pick.

Zoom out to the U.S. and you see each track's ceiling. From edu.vlsi.kr's salary-evidence pages, which collect employer-disclosed posting ranges:

• RTL design: Apple ASIC Design and Integration Engineer, USD 184,700–324,800 base. Synopsys Senior Staff RTL Design Engineer (LPDDR PHY), USD 138,000–208,000.
• Physical design: Apple SoC Physical Design Engineer (Power Delivery), USD 165,800–292,400. Apple CPU Implementation Silicon Correlation Engineer, USD 181,100–318,400.
• STA: Synopsys R&D Principal Engineer (Static Timing Analysis), USD 191,000–286,000.

All three tracks reach the mid-200Ks base at senior levels. The ceiling is set by level and employer, not by track. "PD pays more" or "design gets the best treatment" has weak support in the global data — at least at the top. Don't play the salary game by track as a new grad. Pick the company first.

Episode 3. Competition Reality — The Gate Comes Before the Track

Look at Samsung's hiring funnel. Fall 2026: the document screen narrows applicants to 8–10x the hiring target for the GSAT aptitude test, and GSAT narrows to 2–3x for interviews (Maeil Business Newspaper). GSAT test-takers are projected at 80,000–100,000. Popular roles run past 100:1 competition; the overall average sits around 30–50:1 (job-community estimates — not official).

Here's the cold fact: the GSAT doesn't care about your track. Design, verification, or PD — everyone passes through the same document screen and the same aptitude test first. "Verification is less competitive so it's easier" is half true at best. Track-level headcount differs, but Samsung's first gate is track-agnostic. Real track competition starts at the interview.

And the interviews are completely different per track. RTL design interviews test digital-logic and microarchitecture thinking — blocking vs non-blocking, FSM design, pipeline hazards. Verification interviews test how you'd break things — coverage-closure strategy, UVM testbench structure, the limits of constrained random. PD interviews test PPA trade-off instincts — how floorplan choices hit timing, CTS skew management, IR drop mitigation. edu.vlsi.kr's interview question bank (interviews page) publishes 3,600 concept-based questions across RTL2GDS, STA, RTL design, verification, DFT, analog, and process roles. Testing yourself against them before applying is the fastest track-fit diagnostic there is.

Fabless companies and design houses are different again. No GSAT-style filter — straight to technical interviews. But they read portfolios. An RTL applicant with a RISC-V core or FPGA project on GitHub, a verification applicant with a UVM testbench or cocotb environment, a PD applicant with OpenROAD/OpenLane place-and-route results. What a company buys from a new grad isn't "potential" — it's evidence. That holds across all three tracks.

Episode 4. Five Years Out — Where the Tracks Diverge

Year five. The three career arcs split like this.

RTL design → architect track. Five years in, the designer draws microarchitecture, writes specs, and decides what gets built. The ceiling is the highest — SoC architect, fellow level. But seats are few. One or two architects per project; everyone else stays a block owner. Design's risk is its "small elite" structure: hard to enter, narrower to climb.

Verification (DV) → methodology leadership. Five years in, the verification engineer defines UVM methodology, formal verification flows, and coverage signoff criteria. Verification's strength is portability. Methodology doesn't care about the company or the project — today's memory-controller verifier is tomorrow's AI-accelerator verifier. Stack specialties like formal, emulation, or PSS (Portable Stimulus) and the price goes up. With first-silicon success at 14% (2024), the market value of a "verification lead who guarded the tapeout" keeps rising.

PD → implementation/STA lead. Five years in, the PD engineer owns timing closure. Floorplan to CTS to routing to physical signoff — master of the last gate before silicon. PD's strength is irreplaceability. At 11pm three months before tapeout, when timing won't close, few people can solve it. That scarcity is the price tag — it's why Apple's CPU implementation range runs USD 181,100–318,400. The weakness: skills are tightly bound to EDA tools and process nodes — when the tool changes, you relearn.

The work-life truth, too. All three tracks do late nights before tapeout — just in different patterns. RTL design: spec churn and ECO loops — "retape yesterday's RTL today." Verification: the infinite regression-and-debug loop — fix one bug, find two. PD: the timing-closure hell of the final three months — fighting physics. No track has good work-life balance. PD breathes after tapeout, verification stays steadily busy, design peaks early. Pick against your own stamina pattern — that's the realistic move.

Episode 5. The Playbook — Whichever Door You Entered, Learn From the Front

Now the core. The entry point is luck. You might enter through verification because that's where the headcount is, or get lucky with design, or start in PD. But learning order is a choice. Whichever door you walk through, keep the front-to-back order: RTL → verification → synthesis/PD → STA/signoff. Touch the whole flow.

Case A. You joined as DV — write RTL. The classic trap for verification engineers: becoming someone who only reads other people's RTL and can't write their own. The fix is simple. Keep the RTL of the block you're verifying open beside you, and on weekends, rewrite it from scratch. Implement the same function from the spec alone, then formally compare your RTL against the original. Write the testbench for your own RTL in SystemVerilog or cocotb too. Six months turns you from a reader into a writer. A three-year verification engineer who can also write RTL is rare — design teams covet them.

Case B. You joined as RTL design — learn verification. The designer's trap: believing your own RTL is correct. Write a UVM testbench for a block you designed and chase 100% coverage. Run constrained-random stimulus — it will find the corner case you missed. That's the moment you understand why verification is 55%. A designer who knows verification writes different RTL: synthesis-friendly coding, CDC handling, DFT-aware structure — only designers who know verification and the back end can do that.

Case C. You joined as PD — read RTL. The PD trap: becoming someone who only sees netlists. When a timing violation fires, don't just stare at the netlist — trace back to the RTL source of that path. Understanding why a path is critical from the RTL structure changes the quality of your ECO and restructuring proposals. And learn synthesis first — you can't really see PD until you can read Design Compiler/Genus reports. A three-year PD engineer who reads RTL and runs synthesis takes the shortcut to STA lead.

Three shared assignments, in order: 1. Take one RISC-V core end to end. Grab an open-source core like Ibex, read the RTL, write a testbench, run place-and-route with OpenROAD. edu.vlsi.kr's Engineering page catalogs open designs — OpenTitan, Ibex, VexRiscv. One core shows you the language of all three tracks. 2. Work the 3,600 interview questions by track — edu.vlsi.kr's interviews page. Solve sections outside your own track too. A verification engineer who can solve PD questions — that's front-to-back. 3. Read tapeout postmortems. Behind every successful chip there's a "verification saved it" or "PD held the line" story. Learning from other people's tapeouts is the cheapest tuition there is.

Keep Going on edu.vlsi.kr

Dig deeper into the three tracks on edu.vlsi.kr. All links verified live (2026-10-11).

• RTL design salary evidence — Apple and Synopsys employer-disclosed ranges for the global price of RTL design. The source of this article's Episode 2 numbers.
• Design verification salary evidence — the DV role family definition and related roles (UVM, Formal, Emulation). Official posting ranges are still being compiled — the speed at which this page fills up is itself a barometer of DV demand.
• Physical design salary evidence — Apple's disclosed PD and CPU implementation ranges. Check here if you're curious about PD's ceiling.
• STA vs PD for new grads — Q&A — compares daily problem types, ownership boundaries, and tool exposure between STA and PD. Required reading if you're torn between the two.
• Interview question bank — 3,600 public concept-based questions, by track and difficulty. Use it for the self-diagnostic in Episode 3.
• Semiconductor hiring radar — posting monitor. Build the habit of checking which track's headcount is moving.

Chase's Take

Full disclosure: I started in PD. At SiFive Korea (now SEMIFIVE), I was a physical implementation engineer with full RTL-to-GDS ownership across Samsung 5nm to 14nm, 5+ tapeouts — chips like Rebellions ATOM, FuriosaAI WARBOY, and RHEA passed through my hands. Back then I believed PD was the best. Nobody knows the joy of a tapeout all-nighter like PD does, I thought.

Today I'm a Staff Product Engineer at Synopsys building PrimeTime/PrimeShield/PrimePower — STA and signoff tools. A back-end tools company, in other words. It may sound ironic, but that's exactly why I'm more convinced: juniors must learn from the front, no exceptions.

The scariest moments in my PD days were when a timing violation's root cause sat in the RTL structure. A PD engineer who only reads netlists can't solve that. Because I could read RTL, I could say "this path should never have been structured this way in the first place" — and that separated me from an average PD engineer. Now, building STA tools, I can read customer problems because my body remembers how timing closure blows up on the PD floor. A back-end engineer who knows the front end and one who doesn't are different professions.

That's why this series argues "learn from the front." RTL first, then verification, then synthesis/PD, then STA/signoff. This order isn't a preference — it's the order chips get built in. Learn in the order chips are built, and wherever you stand, you can see both directions.

One last word for new grads. Debating "design vs verification vs PD" is fine — but don't spend six months on it. Walk through the open door, then fill in the front steps behind you. What sets your price in five years isn't your first job title — it's how much you learned outside your first job title. Touch the whole flow. That's not a slogan; it's a survival strategy.

FAQ

Q1. If DV has the most headcount, shouldn't everyone just go into verification? More headcount means more opportunity, not less difficulty. Verification is the discipline of proof — it demands logical rigor and a separate skill set (UVM, formal, coverage). The wider the door, the more it rewards those who prepared for that door. Walk in unprepared and you'll still be rejected.

Q2. Is it true that RTL design is the hardest and best-compensated? Half true. Design is hard to enter (small elite teams). But U.S. employer-disclosed ranges show all three tracks reaching mid-200Ks base at senior levels. The ceiling is set by level and employer, not track.

Q3. People say AI will replace PD. True? AI and automation are eating PD's repetitive work — initial placement, routing. But closure judgment, PPA trade-offs, and tapeout accountability aren't automatable. If anything, the scarcity of "the PD engineer who solves what tools can't" is rising. Become a closure owner, not a tool operator.

Q4. Is learning front-to-back realistic as a new grad? Not alongside your day job at full intensity. Do your job — and fill the front steps as side projects. A verification engineer writing one RTL block on weekends; a PD engineer reading the RTL of their assigned block. Six months turns a reader into a writer.

Disclaimer: This is not career advice. Salary and hiring figures are estimates and vary by individual and employer. Always check official job postings before deciding.