Is a lower CTE always better for a glass-core substrate?

The photograph above shows the die-assembly side of an Intel glass-substrate test package disclosed in 2023. Its upper surface supports chips; its underside connects to a motherboard. These interfaces meet different materials. Choosing how far to reduce thermal expansion means considering the die-side and board-side joints together. Intel photographs and description

That choice gets harder as packages grow. In its research release dated 2026-09-18, TrendForce identified larger AI chip packages as an important development direction. This market observation does not establish production readiness or reliability for a particular glass substrate. It does explain why joints farther from a package's center deserve attention. TrendForce research

VLSI Korea view: Low thermal expansion is an advantage of glass, but it does not help every joint in the same direction. The relevant choice depends on which interface must accommodate the mismatch.

The top and bottom of a package face different problems

A substrate supports chips and routes signals and power. The glass core is its central structural layer, with dielectric and copper routing layers built on both sides. Metal formed inside holes through the glass provides through-glass vias, or TGVs. The glass does not become electrically conductive; the metal paths connect its two faces. IEEE EPS technical material

Small, closely spaced joints sit near the chip. Larger solder-joint arrays connect the package underside to the printed circuit board, or PCB. The BGA, short for ball grid array, in the next photograph is that lower connection surface. Real packages can include interposers or silicon bridges, so the simplified two-interface structure used below is not a cross-section of Intel's test package.

Materials lengthen at different rates when heated. The coefficient of thermal expansion, or CTE, describes that rate. A value of 1 ppm/K means a length increase of 1 part per million for a temperature rise of 1 K. Separate parts can expand independently. Once soldered together, their joints and surrounding structure must accommodate the difference.

Making the substrate expand more like silicon can reduce the mismatch at the die-side connection. If the PCB expands more, however, the mismatch below the substrate grows. An improvement at the top can become a problem at the bottom. An open paper by Unimicron researchers analyzes these interfaces separately. IMAPS 2024 paper

The relevant CTE is not just the bare glass value

“Glass has low thermal expansion” leaves out two distinctions. Different glass compositions have different coefficients, and a completed substrate containing copper and dielectric layers behaves differently from bare glass. SCHOTT lists AF 32 at 3.2 ppm/K and AS 87 neo at 8.7 ppm/K over 20–300 °C. Those are properties of the specified glasses, not effective package values or constants valid at every temperature. SCHOTT material data

An effective CTE for a finished substrate must account for layer thickness, stiffness, routing construction and temperature-dependent properties. One layer cannot expand freely when other layers constrain it. Substituting the bare glass number for the entire stack therefore misses part of the mechanics. Organic materials can also behave differently in-plane and through their thickness.

Length mismatch and warpage are different quantities. A CTE difference describes how much two unconstrained parts would expand relative to one another. Assembly curvature also depends on layer placement, thickness, stiffness, residual stress and restraints. Changing the copper distribution between the two faces can change deformation even without changing the materials. Halving a CTE does not establish that warpage halves.

Calculate the mismatch at both interfaces

For an illustrative design calculation, assume a silicon CTE of 3 ppm/K and a PCB CTE of 18 ppm/K. Candidate effective substrate CTEs are 4, 8 and 12 ppm/K. These are hypothetical choices intended to expose the trade-off, not measured specifications for three products. Assume uniform heating by 100 K and constant CTEs over that interval.

Set the in-plane distance from the central reference to a die-side joint at 10 mm and to a board-side joint at 40 mm. These are distances to particular joints, not the complete side length or diagonal of a square. The free-expansion mismatch magnitude is δ = |α₁ − α₂| × ΔT × r. This first calculates how differently two unconnected parts would try to expand.

With an effective substrate CTE of 4 ppm/K, the die-side mismatch is |4 − 3| × 10⁻⁶ × 100 × 10 mm = 0.001 mm, or 1 µm. The board-side mismatch is |18 − 4| × 10⁻⁶ × 100 × 40 mm = 0.056 mm, or 56 µm. The lower interface has both a larger coefficient difference and a greater distance from the center.

Raise the effective substrate CTE to 8 ppm/K and the die-side mismatch becomes 5 µm while the board-side mismatch falls to 40 µm. At 12 ppm/K, the values become 9 µm and 24 µm. Lowering the substrate CTE improves the upper interface's expansion match while worsening the lower one. None of these candidates minimizes both.

This calculation identifies the unfavorable interface and useful design sensitivities. In an assembly, solder, substrate and die deform together, and temperatures need not be uniform. Turning these numbers into actual joint displacement, stress or lifetime requires structural analysis and testing. Solder can retain inelastic deformation through thermal cycles; it does not behave like a simple elastic spring.

Comparing 1 µm with 56 µm is still insufficient

The height available to accommodate lateral movement differs between interfaces. A thin joint tilts more for the same lateral motion. Add assumed joint heights of 50 µm at the die and 500 µm at the board. Dividing relative displacement by height, δ/h, provides a geometric screening indicator. It is normalized free-expansion mismatch, not equivalent inelastic solder strain.

For the 4 ppm/K candidate, the indicators are 1/50 = 0.020 at the die and 56/500 = 0.112 at the board. For the 8 ppm/K candidate, they are 5/50 = 0.100 and 40/500 = 0.080. A very short die-side joint can become a constraint even while the board-side absolute displacement remains larger. These indicators cannot compare lifetimes or establish the middle candidate as the optimum: joint materials, shapes and support conditions differ.

Package size changes the result again. At fixed CTE and temperature rise, moving a joint from 20 mm to 40 mm from the reference doubles the free-expansion mismatch. Reducing the board-side joint height from 500 µm to 250 µm for the 4 ppm/K candidate doubles δ/h from 0.112 to 0.224. Increasing lateral dimensions while shortening joints can erode the benefit of a material improvement.

Published research provides a counterexample to “lower is better”

The Unimicron IMAPS 2024 study compared glass-core and organic-core substrates in the same basic structure. It used a 10 × 10 mm chip, a 20 × 20 mm package substrate and thermal cycling between −40 °C and 85 °C. Finite element analysis, which divides a structure into small elements to calculate deformation, examined die-side microjoints and PCB-side joints separately.

Under those conditions, the glass-core structure reduced accumulated inelastic strain in the die-side joints but increased it at the PCB-side connection. That does not establish that glass substrates are inferior. It is a counterexample showing that the direction of improvement can reverse between interfaces. Its test structure does not supply a lifetime multiplier for a large AI package. Study geometry, conditions and conclusions

A separate open study by Wang and colleagues in 2021 connected testing and simulation for a fan-out package using a glass substrate. Glass CTE, joint-pad geometry and buffer-layer dimensions all affected reliability. Joint geometry cannot be postponed as an unrelated problem after selecting a material-table value. The study's small package and test conditions also differ from the illustrative calculation here. Original paper

VLSI Korea view: Low warpage, small free-expansion mismatch and long solder-joint life are different metrics. A component-level improvement needs separate verification after board assembly.

Match the expansion, or provide a way to accommodate it

The first option is to adjust the substrate's effective CTE. Whether it should sit closer to silicon or to the PCB depends on joint height, distance and reinforcement. Instead of searching only for glass with the closest match to silicon, determine how the full stack reaches its effective value. The selected construction must also satisfy routing-density and dielectric requirements, so mechanics cannot be optimized in isolation.

The second option is to distribute deformation beyond individual joints. Underfill, the resin filling the die-to-substrate gap, provides a surrounding load path. It does not eliminate all deformation. Its stiffness, expansion and adhesion become part of the structure, which means reinforcement at the die interface cannot simply be copied to the board interface.

The third option is to change dimensions and joint geometry. In the calculation, reducing distance or increasing height lowered the normalized mismatch. Real choices are constrained by I/O count, routing length, assembly spacing and package height. Fitting the same number of connections into a smaller area requires finer pitch and reconsideration of joint shape and assembly conditions. Shrinking the package is not a free remedy either.

Finally, examine failure of the substrate itself. Interfaces between glass and routing layers, diced edges and metallized vias create problems distinct from solder fatigue. IEEE EPS technical material explains the need to manage stack stress and edge microcracks together. Even after improving solder joints, glass-edge cracking or metal adhesion can become the limiting mechanism. Mechanical reliability material

Move the question from material purchasing to assembly validation

This changes how to read a substrate proposal. First establish whether its CTE describes bare glass or the completed stack. Then use the actual die, board, joint locations, heights and temperature history to identify the loaded interface. Finally, connect assembly warpage and joint damage through analysis, and compare thermal-cycle tests under matching boundary conditions. Placing pass counts from different tests side by side does not establish equivalence.

Testing should track both electrical continuity and where damage begins. Connecting joints into a series path and monitoring resistance can reveal an emerging open circuit. Failure-location analysis checks whether the model identified the weak region correctly. Comparing testing with simulation, as Wang and colleagues did, supplies the structure-specific evidence needed to use a prediction model.

The industrial capability extends beyond supplying glass sheets. Glass-composition suppliers, substrate fabricators making routing and vias, assembly providers attaching chips, and system teams setting board and cooling constraints need to share the same boundary conditions. Their combined task is to translate favorable material properties into assembly reliability. This is an interpretation of the engineering roles implied by the two-interface model, not a company revenue forecast.

The right glass-substrate CTE is the one that improves the limiting interface in a particular package, rather than the lowest available number. If a design reduces mismatch at the die, it must also explain how joint height and reinforcement accommodate the mismatch left at the board. That is how a flat substrate becomes part of a reliable system.

Sources and editorial note

Photographs and test-package descriptions come from Intel Newsroom, with editorial-use terms in the Intel Press Hub. Recent industrial context comes from TrendForce, 2026-09-18; the joint-level counterexample from Lau et al., IMAPS 2024; testing and modeling from Wang et al., 2021; material properties from SCHOTT; and substrate processing and cracking from IEEE EPS technical material, 2025.

This technical explanation was prepared from public sources with AI assistance. VLSI Korea operates independently of its operator's employer and claims no firsthand product fabrication or measurement. Original diagrams and the illustrative design calculation are by VLSI Korea and do not represent specifications of Intel's test package. Sources were checked on 2026-10-02.Read our editorial and AI-assistance standards.

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