VLSI KoreaNVHBM Base Die on TSMC 3nm for All Three Suppliers: Why It Is Not a Samsung Loss
NVIDIA standardized only one layer of the HBM stack on TSMC 3nm. Core dies, stacking, and qualification still differ by supplier, and Samsung keeps its turnkey model for standard HBM.
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Key Summary
The short answer: standardizing a process is not standardizing a product. Only the base die process moved to TSMC 3nm. DRAM core dies, stacking, packaging, and yield remain supplier-specific.
NVHBM, unveiled in August 2026, is a custom HBM based on HBM4E. NVIDIA moved its own memory controller into the base die and cites up to 30% more bandwidth and 15% lower HBM power than standard HBM4E.
Samsung accepted the requirement but keeps its in-house turnkey model for standard HBM and custom products for other customers. A backup plan using its own foundry, if TSMC capacity falls short, was also reported.
After the October 18, 2026 reports, the most common reading was simple: Samsung agreed to use a rival foundry, so Samsung lost. That reading treats an HBM stack as a single chip. It is not. An HBM stack combines two very different kinds of die, and only the manufacturing process of the bottom layer was standardized.
HBM stack structure. DRAM core dies sit above a logic base die. Source: VLSI Korea
What was standardized, and what was not
| Layer | Standardized | Still supplier-specific |
|---|---|---|
| Base die | TSMC 3nm process, NVIDIA custom controller design | Implementation detail, power and timing closure, test |
| Core die | 1c-generation DRAM as a generation target | Each vendor cell, circuit, yield and reliability |
| Stacking and packaging | Nothing | TSV, bonding, thermal design, interposer attach |
| Qualification | One design baseline, lower burden | Per-supplier silicon validation and ramp remain separate |
The base die and the core die are different chips
The upper part of an HBM stack stores data: a stack of DRAM core dies. The base die at the bottom stores nothing. It is a logic chip that moves signals between the GPU and the core dies, manages power, and handles test and repair.
Each generation gives the base die more work. HBM4 widened the interface, and NVHBM moves part of the memory controller that used to sit in the GPU down into the base die. The base die is no longer a passive floor. It is a logic design that shapes performance.
That is why the process logic changed. A DRAM process fits the core die. A logic process fits the base die. There was never a technical reason both had to come from the same company fab. Turnkey supply was a sourcing convenience, not a law of physics.
The trap in the phrase 1c for everyone
The reports bundled a second item into the standardization story: core dies on the 1c generation. But 1c is not the name of one process. It is a generation label for 10nm-class DRAM, and the actual cell, transistor, and process differ at every vendor.
Samsung 1c, SK hynix 1c, and Micron 1c are three different processes that share a label. Read timing, refresh behavior, thermal behavior, and yield still have to be measured and qualified supplier by supplier.
The base die works the same way. Sharing TSMC 3nm does not make three implementations identical. How the controller is built, and how power integrity and signal integrity are closed, still separates the parts. A shared process node is a shared starting line, not a shared finish time.
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What NVIDIA gains, and what the three memory makers keep
For NVIDIA this is a qualification-cost decision. If three suppliers ship base dies on three different processes with three different implementations, the validation matrix triples for memory that attaches to the same GPU. One base die design on one process shrinks that matrix and makes it easier to shift volume between suppliers on price and supply.
It is a textbook case of the largest customer setting a supply-chain standard. But the party that sets the standard does not take all the value. Micron has said publicly that custom HBM can command higher prices and margins than standard parts, because a base die with more functions raises the value of the memory product itself.
Samsung should be read through the same structure. What it gave up is base die manufacturing volume on one product, NVHBM. What it kept is core die manufacturing, ownership of stacking and delivery, and the turnkey option on standard HBM and other customers products. The reported backup review of its own 2nm-class process also shows that even the customer setting the standard needs a fallback if TSMC capacity tightens.
Where the real competition moves next
As the base die becomes closer to a common component, differentiation moves elsewhere. First, core die yield. The higher the stack, the more one bad die kills a whole stack, so known-good-die selection and stacking yield decide cost.
Second, thermal and stacking quality. Moving the controller into the base die raises base die heat, and that heat sits directly under the core dies, affecting refresh and reliability. Base die latency and jitter also eat directly into the timing margin of the whole memory interface. The supplier that closes sign-off stably first wins the early ramp.
Third, schedule. A common design cuts validation work, but it also creates a new bottleneck: all three suppliers now share the same TSMC capacity. That bottleneck, paradoxically, leaves a negotiating card with the supplier that holds its own foundry backup.
Chase's Take
Reading this as a defeat story leads to misreading next quarter as well. Watch three numbers instead. When NVHBM ramps in 2027, does Samsung actually book the core die and stacking volume? Does turnkey supply hold on standard HBM? And does the backup in-house process reach real qualification? Those three numbers describe Samsung's position in memory far better than the destination of one base die process.
Note: NVHBM bandwidth and power figures are NVIDIA targets, not measured production data. Process standardization details are as reported on October 18, 2026, and may differ from final company disclosures.
Frequently Asked Questions
What is NVHBM?
NVHBM is NVIDIA's custom HBM unveiled in August 2026. It is based on HBM4E and moves the memory controller from the GPU into the HBM base die. NVIDIA cites up to 30% more bandwidth and 15% lower HBM power than standard HBM4E.
What is the difference between a base die and a core die?
A core die is the DRAM chip that stores data. A base die is the logic chip at the bottom of the stack that connects the GPU to the core dies, handling signal transfer, power management, and test. In NVHBM it also hosts the memory controller.
Is this the first time Samsung uses TSMC?
It is the first time at the HBM manufacturing stage. The two companies previously cooperated on packaging compatibility between GPUs and HBM. This time the base die itself is manufactured on TSMC 3nm.
If all three use 1c DRAM, are the products identical?
No. 1c is a generation label for 10nm-class DRAM, not a single process. Cell structure, timing, yield, and reliability differ by supplier and must be qualified separately.
Does standard HBM also use a TSMC base die?
It depends on the product. SK hynix already uses TSMC 12nm for its HBM4 base die, while Samsung is reported to use its own 4nm for HBM4. The standardization request in this case applies to NVIDIA NVHBM.
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