What Is CFET (Complementary FET)? The Post-GAA Transistor for the 1nm Era

Why CFET Now

As of 2026, 2nm-class GAA (Gate-All-Around) nanosheets are the production workhorse at leading-edge foundry nodes. TSMC N2 has entered full-scale ramp-up, while Samsung Foundry's SF2 is competing in the same generation. But one metric is approaching its limit before the transistor architecture itself: standard cell height.

The industry started at 6T (six-track) in the FinFET era and shrank to 5T with the move to GAA. Going below 4T, however, requires abandoning the planar layout that places NMOS and PMOS side by side. That is where CFET (Complementary FET) comes in. In the long-term roadmaps published by imec, Intel, and TSMC, CFET generally targets the A10 and 1nm regime, with mass production expected in 2029-2031. Since around 2025, CFET test-structure results have appeared with increasing frequency at IEDM and the VLSI Symposium, and the industry is beginning to see SRAM bit-cell results beyond simple transistor demonstrations. In other words, CFET is no longer a 'distant-future candidate.' It has entered consideration as a baseline option for the node after next.

What CFET Is: Stacking PMOS Above NMOS

In simple terms, CFET stacks NMOS and PMOS transistors vertically rather than placing them horizontally. In conventional FinFET and GAA designs, NMOS and PMOS fins or sheets sit side by side within a cell, and the separation between them, known as N-P separation, effectively sets the lower limit for cell height. CFET stacks the two transistors and moves that separation onto the z-axis. This reduces the cell footprint and enables cell heights of 4T or less.

There are two main implementation paths.

• monolithic CFET: NMOS and PMOS channels are formed together through a single epitaxial growth process on one wafer, followed by gates and contacts in an integrated flow. The process flow is relatively simple, but the NMOS and PMOS share the same thermal budget, so both the PMOS SiGe channel and NMOS Si channel must be processed without damage. Doping separation between the two layers and source/drain isolation are also difficult.
• sequential CFET: The lower PMOS is completed first, then an NMOS layer formed on a separate wafer is transferred through bonding and stacked on top. The upper and lower transistors can be optimized independently, providing greater freedom in channel materials. However, all activation and gate-formation steps must be completed within a low-temperature thermal budget of generally below 500°C to avoid damaging the lower transistor while fabricating the upper layer.

Both approaches reuse channel-formation technologies refined for GAA nanosheets and forksheets, with one additional layer stacked on top. CFET is therefore less an entirely new transistor than an evolutionary path that adds another tier along the z-axis to GAA.

Why It Is Difficult: The Problem Is Around the Channel

CFET may look clean on presentation slides, but its real difficulty lies not in the channel itself, but in everything around it.

1) Contacts and MOL (Middle-of-Line) routing. The source/drain and gate connections of both the upper and lower transistors must be routed out of the cell. Paths must bring the upper transistor's contacts downward or out to the side, and the resistance of this contact stack (R_contact) directly determines cell performance. Pairing CFET with BSPDN (backside power delivery) is effectively the baseline assumption, so the upper signal contacts, lower power contacts, and isolation between the two transistors must all fit within one cell.

2) Thermal management. Stacking transistors vertically concentrates their combined heat generation within the same unit area. The path for heat from the upper transistor to escape through the lower layer is narrow, resulting in a higher hotspot temperature at the same clock frequency. No matter how advanced package-level thermal solutions such as Cu pillars and immersion cooling become, cell-level thermal density must still be addressed through thermal-aware placement and power gating at the EDA level.

3) EDA and standard-cell libraries. CFET changes transistor topology, so standard cells themselves must be redesigned. PMOS and NMOS layer positions, pin access, and M0/M1 routing rules all change. RC extraction models, device models succeeding BSIM, and SPICE libraries must all be rebuilt. For PnR tools to support them, another collaboration cycle is required between Synopsys, Cadence, and the foundries. This is one of the most common bottlenecks for nodes approaching volume production.

4) Yield and testing. Stacking two transistors in one cell means that if either one fails, the entire cell fails. Under the same defect-density assumption, the architecture increases cell-level yield loss. DFT methodologies for diagnosing the upper and lower layers independently must also be refined.

Who Is Ahead: The imec Hub and the Big Three Foundries

At this stage, CFET is an R&D technology, not a production technology. Leadership is therefore measured not by production market share, but by the specificity of published demonstrations and roadmaps.

• imec: It is effectively the hub of CFET research. It has actively promoted the CFET concept since around 2018 and updates both monolithic and sequential demonstrations at IEDM and the VLSI Symposium each year. Its member companies, including Intel, TSMC, Samsung, and SK hynix, all receive access to imec's results.
• Intel: After applying RibbonFET, its own name for GAA, first at 18A, Intel has publicly stated that it is evaluating CFET for subsequent nodes. It has also presented CFET structure results from its own R&D chips at conferences including IEDM.
• TSMC: While unveiling its A14 and A10 roadmaps, TSMC has discussed CFET as a transistor candidate for that timeframe. Based on press reports, many analyses suggest that it is prioritizing the monolithic flow over the sequential approach.
• Samsung Foundry: As the first company to put GAA into mass production, Samsung is also actively researching CFET as the next step. It continues to publish results through joint work with imec and its own SAIT (Samsung Advanced Institute of Technology) channels.

On the equipment side, ASML (High-NA EUV), Applied Materials and Lam Research (epitaxy and etching), Tokyo Electron (coaters and developers), and bonding-equipment suppliers EV Group and SUSS hold key positions in the sequential CFET scenario. Which camp's strengths CFET ultimately favors is also a question of which equipment ecosystem matures faster.

Korea Perspective: Essential for Samsung Foundry, Indirectly Relevant to SK hynix

From Korea's perspective, CFET has two distinct implications.

For Samsung Foundry, CFET is a technology it must secure. Even if it narrows the gap with TSMC to some extent at 2nm GAA, missing the timing of CFET adoption and the yield curve in the 1nm regime would put it another generation behind. The device R&D capabilities of its own SAIT and the pace of collaboration with EDA partners Synopsys and Cadence will determine when its cell libraries are ready. Because the choice between monolithic and sequential CFET may also depend on the strengths of its equipment and materials ecosystem, this is closer to an industrial-policy decision than a simple device decision.

SK hynix does not manufacture logic transistors directly. However, as outsourcing base dies to foundries, especially TSMC, becomes established after HBM4 and HBM4E, access to CFET nodes will directly affect the controller complexity of those base dies. Even memory companies now need to monitor the progression of logic transistor nodes.

For Korea's equipment and materials ecosystem, the key question is how far domestic suppliers can catch up in areas where CFET raises the requirements, including channel epitaxy, low-temperature bonding, contact metals, and EUV mask blanks. Frankly, the critical equipment in these fields remains dominated by companies from the United States, Japan, and the Netherlands, while Korea is closer to trying to establish positions in supporting processes.

Watch Points: What to Look for Over the Next 6-12 Months

CFET is a technology aimed broadly at around 2030, but several meaningful signals could emerge over the next 6-12 months.

• IEDM 2026 / VLSI Symposium 2026 presentations: How far imec and the major foundries advance monolithic CFET SRAM bit cells and sequential CFET ring-oscillator results.
• Full TSMC A14 announcement: A14 is likely to use second-generation GAA, but the key question is whether TSMC explicitly mentions CFET for the subsequent A10 node.
• Greater detail on Intel's CFET roadmap: Whether CFET becomes an actual product node in the next generation after 18A volume-production stabilization, following 14A.
• EDA tool support announcements: When Synopsys and Cadence formally support CFET standard cells and PnR flows. Given the pattern of such announcements arriving 1.5-2 years before volume production, they can help estimate the timing.
• High-NA EUV entering volume production: As CFET reduces cell height, it requires smaller pitches, directly increasing dependence on High-NA EUV.

FAQ: Common Points of Confusion

Q. What is the difference between CFET and GAA? GAA changes the structure so that the gate surrounds the channel on all sides, but NMOS and PMOS remain side by side. CFET adds another step by stacking the two transistors vertically to reduce cell height itself.

Q. Does CFET need to be paired with BSPDN? Almost certainly. If power lines remain above the cell while contacts must also reach the upper transistor, routing becomes effectively impossible to close. CFET routing becomes reasonably manageable only after BSPDN moves the power grid to the backside.

Q. Which will win, monolithic or sequential? Monolithic has the advantage in process simplicity, while sequential provides greater freedom in channel materials. Based on publicly available results so far, neither approach is dominant. Different companies are likely to make different choices depending on their equipment and materials strengths.

Q. When will volume production begin? Public roadmaps generally point to 2029-2031. However, if EDA, yield, or contacts fall behind, the pattern in this field is for deployment to slip by one generation, or about 2 years.