DAC 2026 Company Materials: What Synopsys, Cadence, Siemens and NVIDIA Brought
What did major companies actually bring to DAC 2026? This index separates official material, engineering scope, evidence level and the next reader check.
🆓 Free article · Anyone can read this article for free
Read this first
- Big three EDA: Synopsys foregrounded agentic workflows, multiphysics and 3DIC/HBM; Cadence AI super-agents across design, package and PCB; Siemens Fuse EDA AI, agentic verification and 3D IC.
- System companies: NVIDIA connected GPU-accelerated EDA and autonomous flows, Intel heterogeneous integration, and Microsoft the EDA gaps in building high-performance AI accelerators.
- Korea-relevant material: Samsung and SK hynix appear in verification, silicon-lifecycle, memory and ECC-oriented program contributions; AMD/TSMC in 3D integration and test; Keysight in chiplet interconnect, RF and model extraction.
- Evidence rule: An event page establishes scope, a talk page intent, a paper or slide disclosed method and result, and independent reproduction transfer. They are not treated as equivalent.
A list of companies that attended DAC becomes a booth directory. This review indexes technical materials instead. It separates official conference landing pages, newsroom posts, DAC session pages and final-program contributions, then records what each source discloses and which engineering evidence remains missing.
1. The first index contains 11 material records across four groups
The curated set contains three EDA-vendor records, four chip and system records, three memory/foundry/packaging/test records and one test-and-measurement record. It is not a company ranking. Repeated appearances do not inflate a headline score.
A record qualifies when it links directly to DAC through an official page or final-program entry and supports a concrete reader check. Logos, booth locations and slogans without technical scope are excluded. If a talk is listed but no public slides or paper are available, the evidence level remains “program listing” or “named talk.”

2. Synopsys connects agentic workflows to multiphysics and 3DIC
Synopsys' official DAC page combines agentic workflows with a silicon-to-systems scope and lists Multiphysics Fusion, 3DIC/HBM routing and power-ground bump optimization. The technical direction goes beyond generating an RTL file: an engineering agent is expected to coordinate solver state across timing, power, package and thermal domains.
The event page and demo agenda do not disclose full autonomous-engineering success rates. Comparison requires the same design, PDK, constraints, tool versions, compute budget and human-touch policy, plus total-task denominators, failure, escalation, rollback and signoff correlation. Because the author is employed by Synopsys, this material is explicitly held to the same evidence level as every other vendor.
3. Cadence presents super-agents across design, verification, package and PCB
Cadence's official DAC blog describes AI super-agents crossing design, verification, implementation, package and PCB workflows. Read together with the autonomous virtual engineer newsroom announcement, the message is orchestration across domains rather than a point-tool copilot.
The production question is constraint handoff, not the label “autonomous.” A floorplan move can alter timing, SI/PI, package escape and thermal boundaries. The reader should look for auditable tool calls, preserved assumptions, domain-owner escalation and a complete failure denominator.
4. Siemens EDA combines agentic verification with the system lifecycle
Siemens' official material groups Fuse EDA AI, agentic verification, 3D IC and software-defined systems. For verification teams, natural-language testbench generation is less important than regression closure: was a failure reproduced, root-caused and patched while the full regression, coverage and QoR remained intact?
All three EDA vendors discuss AI, but their public emphasis differs. Synopsys exposes multiphysics and 3D system coupling, Cadence cross-domain super-agents, and Siemens verification plus system lifecycle. The figure compares public workflow boundaries, not product quality.

5. NVIDIA, Intel, Microsoft and IBM push EDA toward system design
NVIDIA's official DAC schedule connects GPU-accelerated EDA, an autonomous-flow collaboration with Siemens, TOPCELL research, and AI supercomputing for design. GPU solver acceleration, model capability and full-flow productivity are distinct claims and should not be collapsed into one speedup.
Intel's official session frames heterogeneous integration as an engine of AI performance, while Microsoft's session addresses EDA opportunities encountered in high-performance AI accelerators. IBM appears in the final program through a scaling SKYTalk and verification or research contributions. These begin at the named-talk level; delivered slides and public papers are required before evaluating measured examples.

6. Samsung, SK hynix, AMD/TSMC and Keysight expose implementation boundaries
The final program shows Samsung contributions around verification, silicon lifecycle management and memory-oriented research, and SK hynix contributions involving BCH-ECC/CRC validation and memory or inference engineering. We do not summarize results from the listing alone; each item must be tied to exact authors, a public manuscript or slides, and disclosed silicon or process conditions.
The AMD/TSMC 3D heterogeneous-integration and test panel points to known-good die, thermals, test access, repair, yield and cost. Keysight's official page covers AI-assisted RF and microwave design, chiplet interconnect, compact-model extraction and RTL glitch power. Model range and measurement correlation determine signoff value.

7. We use a five-level ladder for company material
A booth or event agenda establishes topics and demos. A named talk page establishes speaker and intended subject. A public slide deck or paper exposes method, disclosed setup and claimed result. A customer case can establish a bounded production context. Independent reproduction can test transfer to a new design.
A higher level does not mean the entire product is better; it means one claim has deeper public evidence. A low-level but promising direction is not dismissed. The rule simply separates what is currently known from what should be checked next.

8. Agentic EDA claims need six fields across task, baseline and outcome
The task record should identify the design stage, block or full-chip scope, automated actions and remaining manual work. The baseline needs the same PDK, constraints, tool versions and compute budget. Outcomes need the total denominator, failure and escalation rates, QoR and regression deltas, and reproducible artifacts.
Without those fields, compare direction and scope, not cross-company performance. A customer logo, single success case or curated demo cannot be expanded into a workflow success rate. If an agent relaxes constraints or deletes tests to pass, its speedup is invalid.

9. The efficient reading order moves from event page to reproduction
First collect session names, speakers and public links from official DAC and company pages. Second freeze claim wording, workflow boundary, version and date from the named technical page. Third extract baseline, denominator, failures and limitations from public papers, slides or recordings. Fourth seek customer or independent evidence for transfer and production boundaries.
Finally update the ledger after the event. The useful record is not the marketing headline on DAC week, but what public slides, papers, customer data and documentation actually added. This company-material section will be standard in future VLSI, Hot Chips, IEDM, ISSCC and related conference reviews.

Bottom line: DAC 2026 company materials converge on autonomous or agentic workflows, cross-domain closure, 3D integration and AI-system co-design. The meaningful difference is which workflow boundary each company disclosed and how far its evidence progressed. Readers should ask for task, baseline, denominator, failure and signoff boundaries.
Sources
- Synopsys at DAC 2026
- Cadence agentic AI vision at DAC
- Cadence autonomous virtual engineer announcement
- Siemens at DAC 2026
- NVIDIA at DAC
- Intel heterogeneous integration session
- Microsoft AI accelerator EDA session
- Keysight at DAC 2026
- DAC 2026 official program PDF
Editorial note: Official programs and company primary materials were structured with AI-assisted drafting and then passed through VLSI Korea evidence, visual and release gates. A program listing does not prove performance or production readiness. Corrections: [email protected]. Reproducible files: company-material index · DAC 545-title ledger · full source ledger.
Disclosure
This article is for information only and is not a recommendation to buy or sell any security. It is based on public materials and may contain errors in the sources or preparation. The author is employed by Synopsys, and VLSI Korea is operated independently of the employer. Company materials were reviewed under the same evidence standard, and the employment relationship did not determine editorial ranking or conclusions. Investment decisions and their outcomes remain the reader's responsibility.