Hold Timing Fixes in Depth: Detours, Crosstalk, Clock ECOs and the Setup Cost

Fixing hold means preventing the earliest new data from arriving too soon. The difficult part is that the same change can also move the latest data, other fanouts, neighboring nets and the timing of the next register.

VLSI Korea view: A good hold ECO does not insert the most delay. It obtains the required minimum delay with the smallest maximum-delay cost and the narrowest affected path set.

size_cell and insert_buffer are starting points. Real closure also involves delay-cell location, gate-input timing arcs, fanout isolation, metal layers and vias, routing detours, clock-leaf arrival times and scan connections. A modification that looks slower can even become faster after extraction.

This article focuses on synchronous ASIC register-to-register paths. Reducing setup slack is different from increasing the capture cell's own setup-time requirement. Both can happen, and they must be distinguished. Library setup/hold constraints can also be negative; the positive windows in an explanatory diagram are not fixed properties of every FF. FPGA documentation is used only as evidence that implementation tools actually use routing detours; its numerical thresholds and routing commands are not ASIC rules.

Fix the signs before changing the clock

Let L be the launch register's clock insertion delay and C the capture register's. For a simplified path between rising-edge flip-flops at the same frequency, with same-edge hold and next-edge setup checks, the relationships are:

Hold slack = L_early + t_cq,min + d_min − C_late − t_hold − U_hold + P_hold

Setup slack = T + C_early − L_late − t_cq,max − d_max − t_setup − U_setup + P_setup

Here d includes combinational-cell and net delay, t_cq is launch clock-to-Q, and T is the period. U is the uncertainty applied to the respective check; P is the permitted common-clock pessimism correction. Do not add P again when using clock delays already corrected in a report. Use delay values with the appropriate derating and SI treatment, and do not mix terms from incompatible reports. AMD's slack definitions show why capture-minus-launch skew helps setup and hurts hold.

With clocks and cell constraints unchanged, increasing data delay improves hold and worsens setup. However, the increase in the hold corner need not equal the increase in the setup corner. Gaining 30 ps in a fast view does not imply spending only 30 ps in a slow view.

Advancing the capture clock or delaying the launch clock helps this path's hold and hurts its setup. Moving both clocks equally leaves skew unchanged in this simplified model. In a real design, slew, OCV, shared clock segments and SI may also change, so equal nominal-latency changes do not guarantee cancellation.

T does not appear in the same-edge hold equation. Lowering frequency therefore usually does not repair this violation. Generated clocks, opposite edges, latches, I/O paths and multicycle relationships require the actual launch/capture edge relationship to be reconstructed. The earlier setup and hold introduction covers the foundations.

Establish that the path really needs a physical repair

Trying to erase a negative number immediately can hide an incorrect clock relationship under thousands of buffers. First identify the mode, startpoint and endpoint, rise/fall transition, source/generated clocks, latency and propagation, uncertainty, min/max I/O delays, exceptions, and library/RC corner.

Common sources of an excessive hold requirement include a multicycle setup exception whose hold relationship does not reflect intent, case analysis that enables a nonfunctional path, an incorrect clock-mux relationship, or an omitted test mode. AMD UG906 explains how incorrect multicycle constraints and excessive skew can cause hold detours that damage setup. Its FPGA-specific thresholds should not be imported into an ASIC flow.

Check whether CPPR/CRPR and approved path-based analysis remove impossible pessimism. This corrects an analysis model; it does not create physical delay. As the clock-network pessimism paper explains, the correctable common segment is path-specific. PBA does not guarantee that every violation disappears or that every reported value improves.

Adding a false path or reducing uncertainty is justified only by functional or methodology evidence. A delay ECO cannot synchronize an asynchronous CDC. CDC, recovery/removal, clock-gating checks and minimum pulse width are separate from an ordinary data hold check.

Choose the branch before choosing the buffer

Suppose a driver serves both a fast endpoint B and a setup-critical endpoint C. Inserting a delay cell before their common-trunk split places a new stage on both paths. C may pay the setup cost of repairing B's hold, but the actual net delay change must include the changed loading.

Insertion after the split, on B's branch, narrows the direct effect. It does not provide perfect isolation: the new buffer's input capacitance and its route change the load seen by the common driver, so C's arrival must still be recalculated. “Insert near the capture pin and all other paths are safe” is an approximation, not a guarantee.

If several hold endpoints share a branch and every max path through it has headroom, a shared delay stage may be preferable to many endpoint buffers. Conversely, if several launch paths reconverge at one endpoint and even one has tight setup, insertion immediately before that endpoint can still be unsafe. Inspect both the fanout and fanin path sets.

The net increase after buffer insertion is not the buffer's library delay. The original driver may become faster when isolated from a large wire/load, and a stronger new stage may reduce downstream net delay. That is why repeaters help long RC wires. A buffer intended for hold can add less delay than expected or even accelerate the full path. Compare cell delay, net delay and slew before and after insertion.

The OpenROAD resizer documentation distinguishes buffering to reduce long-wire RC delay from hold repair. It describes hold repair with propagated clocks after CTS and consideration of setup. An automated ECO must likewise evaluate the complete result, rather than assume that adding a cell adds an equal amount of path delay.

Cell changes include more than drive-strength sizing

A dedicated delay cell can be a useful candidate before a general-purpose buffer. Its internal stages and devices are designed to provide delay. The public SKY130 delay-buffer documentation describes a multistage delay cell with a specified internal gate length. This establishes that such cells exist, not that they are optimal in every process. Footprint, min/max arcs, rise/fall behavior, output slew, variation models and placement space determine suitability.

Downsizing drive strength can increase output resistance and delay. However, lower input capacitance can accelerate the preceding stage, while slower output slew changes downstream delay and endpoint constraints. Check whether the complete minimum path became slower, not merely the selected cell. Removing a stage from an over-buffered path, or replacing it with a weaker one, requires the same full-path assessment.

A Vt swap or library-supported longer-channel variant changes delay/leakage characteristics while preserving Boolean function. The usual objective is a slower candidate, but an HVT label does not prove increased delay at every corner, slew and load. Footprint, rails, implant/well compatibility, legal placement, dont-use policy and signoff-library coverage still apply.

An inverter pair or function-preserving logic decomposition can add stages. An even number of inversions does not make timing behavior equivalent. Rise/fall paths, glitch propagation, pulse filtering, reconvergence and reset/test behavior can change. Synthesis may also collapse the structure unless the implemented ECO preserves it. Preplaced spare/ECO cells can be useful in a metal-only stage, but only within the available mask, power, connectivity and verification constraints. Equivalence, electrical checks and timing checks are all required.

Equivalent input-pin swapping is a finer adjustment. Boolean-equivalent inputs can have different pin capacitances and internal timing arcs. Moving an early signal onto a slower arc may improve minimum delay, but another input receives the opposite change. Routing, conditional arcs, unateness and rise/fall behavior must be checked. This does not authorize swapping logically different pins such as a mux select and data input. The ISPD local-transformation paper treats pin swapping, sizing and buffering as interacting optimizations. Using those choices in the hold direction is a design-specific decision based on the actual library and paths.

The launch or capture flip-flop itself can also change. A launch FF with larger t_cq,min or a capture FF with a smaller hold requirement may help, but can bring larger t_cq,max or t_setup, more clock-pin capacitance, or different scan/reset behavior. The PieceTimer research examines why setup, hold and clock-to-Q are not entirely independent quantities. Production choices must use the approved characterization model.

Route detours: why extra wire works, and where it fails

Deliberately routing a net around a longer path changes wire resistance and ground/coupling capacitance. This can be attractive when cell space is scarce or the available ECO is metal-only. A published routing patent describes inducing a detour with a routing blockage, then checking secondary violations. Intel's physical-synthesis material also explicitly identifies detoured routing as an FPGA hold-repair technique.

For intuition, consider a uniform RC wire with a lumped receiver load. Its approximate Elmore first moment is τ ≈ R_driver(C_wire + C_load) + R_wire(C_wire/2 + C_load). With a fixed cross-section, wire R and C scale with length, producing a length-squared component in the wire term. This helps explain topology; it is not an exact signoff prediction of the 50% crossing delay. A real net with coupling, branches, vias, waveforms and buffers must be extracted again.

Where the extra length is placed matters as much as how much is added. Series resistance near the driver sees the influence of capacitance downstream. A far-end branch detour and a common-trunk detour affect different sink sets and different RC weights. Equal added length does not imply equal added delay.

A tightly folded meander can couple to neighboring nets and to spatially separated segments connected through finite wire resistance within the same net. Points on the same logical net do not necessarily have identical instantaneous voltage. Treating this self-coupling as automatically 0 or as simple ground capacitance can therefore misrepresent the circuit. Use the topology supported by the extractor and delay engine.

Route guides, waypoints, local blockages and ECO rerouting can help implement such a candidate, but the exact mechanism and preservation controls are tool- and version-dependent. A later router may shorten the path again, and DRC repair can alter it. Verify that the extracted route is the route retained in the final delivered database.

Typical detour failure mechanisms include excessive max-delay growth in a setup corner, degraded slew that increases receiver delay, congestion that forces neighboring critical nets to detour, or SI speedup that cancels the expected minimum-delay gain. Cell-free does not mean cost-free.

Finer RC adjustments: layer, width, vias and deliberate loading

The intuition that a lower layer, narrower wire or via-rich route will be slower can generate candidates. It does not establish universal rules such as “lower metal fixes hold” or “wider wire fixes setup.” Sheet resistance, thickness, dielectric environment, spacing, ground/coupling capacitance and actual transitions act together.

Layer reassignment and width changes alter both R and C. A wider wire may reduce resistance while increasing capacitance. Extra spacing may reduce coupling but require a longer route. Moving upward in the stack may add vias that change the expected gain. The public SKY130 extraction rules demonstrate structure-specific resistance and capacitance modeling; their values and permitted structures must not be transplanted into another node.

Via choices and legal metal extensions provide other adjustments. US20200401668A1 describes timing modification using metal extensions and alternate vias, including checks for neighboring critical-net coupling and DRC. It is a published example of an approach, not permission to remove arbitrary vias or increase resistance without qualification. Timing must not override redundant-via, EM or reliability rules.

Deliberately increasing load can slow a driver, but its effects spread easily. Consider it only through approved load/delay structures. Meaningless dangling gates or unauthorized capacitors may be optimized away or cause extraction, LVS and power problems. Every sink on a shared driver, transition quality and dynamic power can be affected.

Cell relocation, branch separation and driver cloning change the load and topology themselves. A setup-critical branch may remain fast while a hold-sensitive branch receives separate drive. But the clone adds upstream fanout; a register clone also adds clock, reset and scan load. Without enough space, legalization can cause greater timing damage than the original problem.

Crosstalk is part of detour delay, not an afterthought

Voltage transitions on an adjacent wire change a victim's current and waveform through coupling capacitance. In representative overlapping-transition cases, same-direction switching can accelerate a victim, while opposite-direction switching can slow it. The former can threaten min-delay/hold; the latter can threaten max-delay/setup. The ICCAD switching-window paper explains why transition direction must be considered together with the intervals in which the nets can actually switch.

A simple capacitive intuition is i_c = C_c × d(V_victim − V_aggressor)/dt. Identical moving waveforms have a small differential-voltage change; oppositely moving waveforms can produce a larger one. This is not a signoff rule that same-direction coupling always equals 0C or opposite-direction coupling always equals 2C. Driver strength, unequal slews and amplitudes, distributed RC and alignment among multiple aggressors are missing from that simplification.

A detour that extends a parallel run beside an aggressor may increase nominal RC delay while increasing SI sensitivity. Moving the victim's arrival can reduce overlap with an existing aggressor or introduce overlap with another window. SI-aware delay and switching windows therefore cannot always be calculated independently in one fixed pass.

“A hold path is fast, so crosstalk can only slow it down” is wrong. Data-path speedup can worsen hold. On the clock network, an earlier launch clock or later capture clock can also hurt hold. The opposite combinations matter for setup. Analyze the relevant worst cases for data and clocks within the approved signoff methodology.

Distinguish a noise glitch on a stable victim from delta delay on a switching victim. A glitch's ability to cause a logic error depends on pulse amplitude, width and receiver behavior. Positive setup/hold slack does not replace noise verification.

Why shielding and spacing can help or hurt hold

Increasing spacing can reduce dependence on an aggressor. A shield reduces some neighbor coupling while introducing capacitance to the shield, consuming routing resources and requiring proper connectivity. The on-chip crosstalk research examines delay/area trade-offs for shielding and encoding. Improvement percentages from a specific bus model are not guarantees for an arbitrary ASIC net.

If same-direction speedup causes the hold problem, reducing that coupling may recover minimum delay. Conversely, reducing the total load can make the net faster and worsen hold. A max-delay improvement from removing opposite-direction slowdown does not establish the direction of the min-delay result.

Practical SI candidates include spacing, shielding, layer changes, shorter parallel runs, rerouting, victim buffering and legal aggressor slew/drive adjustments. Analyze more than the chosen victim: it may itself be another net's aggressor, and weakening an aggressor can break that net's setup. Removing an aggressor through an unsupported false-path assumption is not an SI repair.

Clock ECOs move the problem into neighboring paths

When excessive clock skew is the cause, or several endpoints need coordinated repair, clock-leaf arrival time becomes another candidate. Advancing capture or delaying launch helps the selected hold path. The Synopsys ISPD CTS presentation states these directions and the risk of controlling skew under variation.

With all other terms fixed on the same path, advancing capture by δ improves hold by δ and worsens setup by δ. Pure skew adjustment cannot recover an already exhausted same-path setup budget for free. It may be preferable to a data ECO because its corner sensitivity or affected path set differs, but every connected timing budget remains binding.

Options include clock-leaf sizing, stages and routing; rebuilding a branch with excessive insertion delay; or improving clock topology. They remain subject to clock-cell, NDR, slew, duty-cycle, pulse-width, gating and OCV rules. This is not a prescription to insert arbitrary data buffers into the clock tree.

For A→B→C, advancing B makes capture earlier on A→B, improving its hold and worsening its setup. On B→C, it makes launch earlier, improving setup and worsening hold. If other FFs share the changed branch, the effect can spread across many paths.

The required input to a clock ECO is not just one endpoint's hold margin. It is every incoming/outgoing setup and hold path at the changed leaf, plus shared clock segments. Nominal skew improvement does not establish improvement at every corner. Changing the common segment can also change CPPR. Clock-tree reasoning must include this neighboring-path structure.

Scan hold has a different set of remedies

Treating functional paths and scan-shift paths identically can waste substantial effort. Scan may be dominated by a short Q→SI connection and skew between clock branches. Reviewing scan order and clock-domain grouping, or using a lockup latch/element matched to the actual shift waveform, addresses the DFT structure itself.

For example, a low-level-transparent latch after a positive-edge scan FF, controlled by the launching scan clock, closes at that rising edge, preventing newly launched Q data from immediately reaching the next FF, and can transfer it in the subsequent low phase. The actual protection interval depends on clock skew, duty cycle and latch timing. One latch does not automatically make every domain crossing safe.

Scan reorder is often used to reduce physical distance; the OpenROAD DFT documentation describes placement-based reordering. Shorter wiring can nevertheless worsen hold. A hold-driven reorder must preserve shift min/max timing, domain/edge ordering, lockup requirements, scan-chain definitions and ATPG consistency. Lowering scan frequency alone does not eliminate same-edge hold.

Adding a functional latch, changing to an opposite-edge FF, retiming or adding a pipeline stage is a larger architectural change. Latency, cycle semantics, reset, CDC and DFT can change, so these are not interchangeable with late-stage combinational ECOs. An extra pipeline stage can create new short hold paths.

A 45 ps hold gain can cost 90 ps of setup margin

The following is an illustrative ECO comparison, not a measurement of any process, cell or router. Start with hold slack −32 ps and setup slack +70 ps, and assume clocks, constraints and other effects remain fixed.

Candidate A adds 45 ps to minimum data delay in the hold view and 55 ps to maximum data delay in the setup view. The result is hold +13 ps and setup +15 ps. Candidate B adds the same 45 ps to minimum delay but 90 ps to maximum delay, producing hold +13 ps and setup −20 ps. Calling A a delay cell and B a detour would still not establish that one method is universally superior. Actual library and RC results can reverse the ranking.

For an ECO knob x ≥ 0, assume local hold benefits a_k·x and setup losses b_j·x with positive a_k and b_j. The lower bound imposed by hold deficits and target margins must be no greater than the upper bound allowed by setup budgets after reserves. Equal bounds can be mathematically feasible, but discrete legal cells/routes and electrical limits must still admit a realizable choice. With 0 or negative sensitivity, evaluate the corresponding per-view slack inequality directly instead of using this lower/upper-bound shortcut. If there is no shared feasible interval, adding more buffers cannot solve that restricted problem.

Real ECO sensitivities are not constants. Cell swaps, slew changes, a different critical path, SI-window changes and topology changes can make them discontinuous. This approximation is a way to screen candidates, not a replacement for STA. An infeasible case requires another dimension: branch isolation, a better library candidate, separate setup optimization, clock topology or architecture.

Decompose every possible source of setup damage

Rather than memorize tool options, classify the term in the setup equation that changed. Direct data-path cost, receiver-constraint changes, clock-budget changes, physical side effects and analysis-condition changes can overlap.

ΔSetup slack = ΔT + ΔC_early − ΔL_late − Δt_cq,max − Δd_max − Δt_setup − ΔU_setup + ΔP_setup

Each Δ is a signed change between comparable before/after reports. Decompose the same path in the same view before comparing only whichever path became worst.

Table 1. Setup-risk taxonomy for hold ECO review. Original synthesis by VLSI Korea; direction and magnitude require the actual design context.

The first cost is direct maximum-delay growth; the second is slew. A weaker driver changes the receiving waveform, potentially changing both downstream propagation delay and the endpoint setup constraint. Combining both into “more net delay” obscures the next corrective action. The setup constraint depends on the cell, data slew, clock slew and transition. Do not assume it always changes in one direction. Added antenna-repair diode capacitance and clock-pin loading after an FF swap are easily overlooked examples.

The next cost is shared physical resources. Making room for hold buffers can displace neighboring cells and lengthen an untouched setup path. Added capacitance and switching activity change power; sufficiently large local current changes can affect voltage drop and timing. This does not mean every added buffer creates a measurable IR failure. It explains why voltage-aware verification matters, as discussed in Cadence's timing/power-integrity integration.

Variation and signoff context add another dimension. Changes in stage count and distance can affect AOCV treatment. Statistical flows require examining sigma and correlation as well as nominal delay. Synopsys' AOCV explanation describes logic-depth-dependent path/cell margins. There is no universal rule that an extra buffer improves variation by averaging it out.

Avoid the shortcut that hold is always worst at FF/low temperature and setup at SS/high temperature. The sensitivity reversal documented in temperature-inversion research, RC corners, DVFS, level-shifter/isolation operation and different clock/data sensitivities can move the worst view. Final metal fill, signoff extraction and approved aging/voltage conditions must also be covered when required by the methodology.

Finally, a worse setup WNS after an ECO does not necessarily mean the same path slowed by that amount. A different path may have become worst. Compare identical paths before and after, together with overall WNS, TNS and violating-endpoint counts.

What must be checked before an ECO is finished?

Before modification, save more than the failing endpoint. Preserve min/max reports including full launch/capture clocks, rise/fall transitions, library/RC corners, diagnostic SI-on/off results and the parasitic, constraint and netlist versions. SI-off results isolate causes; they do not replace SI signoff.

After modification, complete legal placement and routing and extract current parasitics. Confirm that the min-delay gain remains and the max-delay cost fits the budget. Expand the checked neighborhood to changed drivers, fanouts, fanins, aggressors and clock branches.

Then rerun setup and hold across the complete approved MCMM set, along with maximum transition, capacitance and fanout; noise; clock pulse-width and gating checks; and recovery/removal where applicable. Logic/netlist changes need equivalence verification, scan changes need scan-chain/DFT validation, and physical changes need the applicable DRC, LVS, antenna and EM checks. A clean STA report is not the whole signoff process.

Commands are subordinate to this verification flow. The legal objects, options and ECO behavior of names such as size_cell and insert_buffer depend on the product and version. Even OpenROAD's public repair_timing -hold requires appropriate libraries, clocks, parasitics and setup-protection conditions. It is not a universal script to paste into commercial tools.

VLSI Korea view: Advanced hold repair is primarily the ability to control the affected path set. Moving from cells to wires to clocks increases the neighborhood that must be verified.

A practical selection order

First remove incorrect constraints, clock relationships and analysis mismatches. Then determine whether the deficit is local or whether excessive skew affects many endpoints. In the latter case, clock-architecture review may be more effective than adding many data buffers.

For local failures, compare branch-limited delay-cell, sizing, Vt and pin-arc candidates. When space or mask restrictions dominate, evaluate route detours, layers, vias and metal extensions, using extracted RC/SI and neighboring setup results. When setup and hold collide within a narrow budget, consider fanout isolation, cloning, clock ECOs and separate setup optimization together.

Treat scan through its clocking and lockup structure, and architectural problems through changes that include latency and verification contracts. Every candidate faces the same questions: Is the earliest data late enough? Are the latest data and neighboring paths still safe? Does that result survive final MCMM, SI and physical signoff?

Sources and scope

Sources checked on 2026-09-17. The ps comparisons are explicitly illustrative calculations, not measurements from a particular PDK, library or customer design. Figures are original VLSI Korea schematics based on public principles. Actual commands, exceptions and margin changes must follow the installed product version, public documentation and approved signoff methodology.

In addition to the direct links above, RC-model foundations are discussed in David Harris' public CMOS lecture, and a public scan-lockup architecture appears in the Hierarchical scan architecture patent. Patents establish that approaches were proposed; they do not establish production performance or universal process rules. This article used AI-assisted research and writing with a separate technical review. It uses no internal PDK or customer information outside the public evidence reviewed.