Setup Time and Hold Time are two of the most important timing constraints in digital circuits:
- Setup Time is the time that data must reliably arrive before the clock edge, and
- Hold Time is the time that data must be held after the clock edge.
If these two conditions are not satisfied at the same time, the circuit can enter a metastable state and malfunction.
개요: Setup and Hold Understood with an Airplane Arrival Analogy
Consider the passenger boarding system at an airport. Planes depart at exactly a set time (the clock edge). Two conditions are required before a passenger can board:
- Setup Time Condition: The passenger must be on the platform 30 minutes before the plane departs (Setup Time). If you arrive 30 minutes before departure? The gate is already closed, and unfortunately, you are too late to board. This is a Setup Violation.
- Hold Time Condition: Passengers must not abruptly leave the plane during the 5 minutes after the plane lands (Hold Time). If they leave just two minutes after departure? It's a Hold Violation.
The exact same principle applies in VLSI design. In order for the input data to the flip-flop to be captured exactly at the clock edge, both of these time windows must be satisfied.
Setup Time: Basic Concepts
Definition of Setup Time
Setup Time (tsu) is the minimum time that the input data to a flip-flop must be stable before the clock edge. Physically, it is the time for the electronic action required for the LATCH circuit inside the flip-flop to correctly capture new data.
For example, consider a flip-flop with a setup time of 1.2 ns. If the clock rising edge occurs at exactly 10.0 ns, the input data must arrive before 10.0 ns - 1.2 ns = 8.8 ns.
Calculating Setup Slack
In Static Timing Analysis (STA), setup slack is calculated as follows:
Setup Slack = Required Time - Arrival Time
= (Clock Time - Setup Time) - Data Arrival Time
- Required Time: The final time the data must arrive (clock edge - Setup Time)
- Arrival Time: The time the data actually arrives
- Positive Slack: Slack is available (safe)
- Negative Slack: Violation
Why setup violations happen
Setup violations happen in the following situations:
- Too much delay in the combinational logic path
- Too short a clock cycle
- Large signal delay due to lack of buffers or inverters in the data path
- Large delay due to Process, Voltage, Temperature (PVT) changes
Hold Time: Basic Concepts
Definition of Hold Time
Hold Time (th) is the minimum amount of time that the input data to a flip-flop must remain stable after the clock edge. While data is captured at the clock edge and stored in internal storage, the input must not change.
For example, consider a flip-flop with a hold time of 0.8 ns. If the clock rising edge occurs at 10.0 ns, the input data should not change by 10.0 ns + 0.8 ns = 10.8 ns.
Calculating Hold Slack
Hold slack is calculated a little differently than in setup:
Hold Slack = Arrival Time - Required Time
= Data Arrival Time - (Clock Time + Hold Time)
- Required Time: Minimum time (clock edge + Hold Time) that data can change: Time at which data from the previous clock cycle arrives
- Positive Slack: Slack (safe)
- Negative Slack: Violation
Mechanism of a Hold Violation
A hold violation occurs when the delay in a combinational path is too short. It sounds paradoxical, but consider the following:
If the data from the previous clock cycle arrives at the next flip-flop too soon, the input of that flip-flop will have already changed immediately after the current clock edge. This can lead to a metastable state because the input changes before the flip-flop can properly latch the current data.
Specifically:
- Prev FF's output changes quickly (short combinational delay)
- Current FF's input changes within the Hold Time window
- Current FF can capture the intermediate state between the old and new values
- Result: Metastable state → Increased convergence delay → Timing issues
Real-world example: Analyzing Setup Time
- Required Time: 5.0000ns → means the clock cycle is 5ns
- Arrival Time: 5.3274ns → data actually arrived at 5.3274ns
- Slack: -0.3274ns → Setup Violation!
How to fix Setup Violation
- Reduce combinational logic delay:# Change the cell in the critical path to a larger size
size_cell u3 BUF4X8 # Existing BUF2X2 → BUF4X8
insert_buffer -place_buffers -cell BUF4 path_name - Increase the clock period: Change clock from 5ns → 6ns
- Add pipeline: Break combinational logic into multiple stages
How to fix hold violation
- Add delay buffer
- Change driving cell: Change a small cell (BUF1X) to a large cell to limit speed
- Relocate combinational logic: Increase delay by physically increasing distance
- Increase load: Add capacitive load to the path
Frequently Asked Questions (FAQ)
1. Can Setup Time and Hold Time be violated at the same time:
Yes, it is possible. For example, they can occur simultaneously due to process voltage temperature (PVT) variations or clock jitter. In this case, there may be a fundamental problem with the design itself.
2. Which is more important, Setup or Hold?"
Both are equally important. Setup violations result in incorrect values being stored because data is not captured properly, while Hold violations result in convergence delays and metastability due to metastable states. Both cause circuit malfunctions.
However, when the chip comes out, Hold time is more important. Timing violations can be fixed by increasing the clock period, but hold time violations have no solution.
3. Does reducing the clock period always cause only Setup to be violated?"
It mainly causes Setup Time to be violated, but Hold Time can also change in special cases. Clock skew, jitter, propagation delay in the clock tree, etc. come into play, so both need to be verified.
4. What exactly is a metastable state?"
It is a phenomenon where the internal state of a flip-flop is stuck in an unstable intermediate state that is neither 0 nor 1. It occurs when a Setup or Hold Time violation occurs, and can take an unpredictable amount of time to converge or not converge at all. In modern circuits, this is the most dangerous timing problem.
5. Are there flip-flops with negative hold times?"
Yes, there are. Some flip-flops in modern technology nodes can have negative hold times, which is an advantage for designers. Negative hold time means that the data is safe to change to some extent after the clock edge. However, the setup time may be more stringent.
고급 개념: Clock Skew and Timing
Effects of Clock Skew
In a real-world chip design, the clock signal does not arrive at all flip-flops at exactly the same time. This is called clock skew:
- Positive Skew: Clock from source FF arrives before destination FF → Worsens Setup, improves Hold
- Negative Skew: Clock from destination FF arrives before source FF → Improves Setup, worsens Hold
Thus, clock tree design is an important part of Setup/Hold optimization.
PVT (Process, Voltage, Temperature) Variation
Real-world chip manufacturing is not perfect: process variations change the characteristics of transistors, voltage drops occur, and temperature variations change delays:
Design should always be validated under worst-case PVT conditions. PrimeTime silences the STA for corners (each PVT combination) to ensure it is satisfied under all circumstances.
Summary
- Setup Time: Minimum time that data must arrive before the clock edge. Slack = Required Time - Arrival Time > must be 0
- Hold Time: Minimum time that data must remain stable after the clock edge. Slack = Arrival Time - Required Time > should be 0
- PrimeTime: Validate setup/hold violations with report_timing, check_timing, report_qor, and analyze paths
- Solution: Setup reduces delay and Hold adds delay. Both are closely related to clock tree design
- Metastable: Worst case scenario of a Setup/Hold violation. Can lead to complete malfunction of the chip and must be removed