industry-research

VLSI-SoC 2026 Attendee Guide: Registration, Program, and Limassol Access

🆓 Free article · Anyone can read this article for free VLSI-SoC 2026 runs from 2026-10-11 to 2026-10-14 at the St. Raphael Resort in Limassol, Cyprus. 2026-10-11 is tutorials day, and the main conference program runs from 2026-10-12 to 2026-10-14. The official program publishes dates and times for keynotes, regular sessions,

Chase Na 나경채

28 8월 2026, 10:27 KST Updated 24 10월 2026, 09:38 KST · 11 min read ·

AI-generated conceptual image - VLSI Korea. Not evidence of the actual St. Raphael Resort or Limassol cityscape.

🆓 Free article · Anyone can read this article for free

VLSI-SoC 2026 runs from 2026-10-11 to 2026-10-14 at the St. Raphael Resort in Limassol, Cyprus. 2026-10-11 is tutorials day, and the main conference program runs from 2026-10-12 to 2026-10-14. The official program publishes dates and times for keynotes, regular sessions, special sessions, the panel, poster displays, and the social program.

As of 2026-08-28, late non-author registration is open from 2026-08-22 to 2026-10-11. The official page does not state a late full-registration amount and directs attendees to the registration platform; only late one-day registration is publicly priced at €300.

This guide uses only public organizer, program, registration, venue, airport, and transport-owner material available on 2026-08-28. It does not infer unannounced talks, launches, attendee access, travel times, seats, prices, or on-site operations.

VLSI-SoC 2026 official date and venue envelope — Official dates and start or end markers separate tutorials day from the 3 conference days. Source: official page. Figure: VLSI Korea.

Fix the event identity and access scope first

Decision	Verified fact	Official owner
Event	34th IFIP/IEEE International Conference on Very Large Scale Integration SoC	VLSI-SoC 2026
Dates	2026-10-11 to 2026-10-14	VLSI-SoC 2026
Venue	St. Raphael Resort, Amathus Avenue 502, 4534 Pyrgos, Limassol, Cyprus	Organizer / venue
Registration state	Late non-author window: 2026-08-22 to 2026-10-11	Organizer
Email	Site publication only; no subscriber email	VLSI Korea policy

The VLSI Calendar record and official conference site identify the same edition, dates, city, venue, and in-person format. The official site describes the event as the 34th edition of the VLSI-SoC series, sponsored by IFIP TC10 WG 10.5, IEEE CEDA, and IEEE CASS.

The official topic scope covers architectures, circuits, devices, design automation, verification, test, and security. A topic list does not guarantee the outcome of an individual talk or a product disclosure at the conference. This guide uses only sessions listed in the actual technical program as schedule evidence.

The event location is identified as the St. Raphael Resort, and the organizer travel page gives the address as Amathus Avenue 502, 4534 Pyrgos, Limassol, Cyprus. The venue's official site confirms the St Raphael Resort & Marina identity, but this guide creates no room assignment beyond what the organizer program publishes.

The VLSI-SoC homepage publishes the organizing committee and sponsor/supporter identities. The general chairs are Tiziana Margaria and Ian O'Connor, while organizer-listed sponsors/supporters include IFIP, IEEE, IEEE CAS, IEEE CEDA, and participating universities. This establishes organizer identity; it is not an endorsement or attendance recommendation.

Registration: do not manufacture the late full price

VLSI-SoC 2026 late registration and access gates — The late full price remains a platform check; the published late one-day price is EUR 300. Source: official page. Figure: VLSI Korea.

The official registration page separates access into full, student, Sunday tutorial, and one-day categories. It states that full registration includes all sessions, symposium proceedings, the program booklet, coffee breaks, lunches from Sunday through Wednesday, the Monday welcome reception, and the Tuesday social event.

Student registration includes all sessions, proceedings, the program booklet, coffee breaks, lunches, the welcome reception, and the social event. It also requires a valid student card. A separate fee-table note asks for proof of student status in the form of a student ID or institution letter sent to [email protected].

Sunday tutorial registration covers tutorial presentations, coffee breaks, and lunch on 2026-10-11. One-day registration covers sessions, proceedings, coffee breaks, and lunch on the chosen day but excludes the social event. The organizer does not frame repeated one-day purchases as the path for non-authors attending more than one day; it points them to full registration.

The early non-author fee window ended on 2026-08-21. As of 2026-08-28, the applicable late non-author window runs from 2026-08-22 to 2026-10-11. The official page does not publish a numeric late full-registration fee and explicitly directs readers to the registration platform, so this article does not reuse the former early prices of €600 or €750 as current prices.

The published late one-day price is €300. One-day registration is limited to non-authors, while authors must use author registration. The registration platform is the final owner for amount, tax, availability, and cancellation conditions; this article does not infer logged-in information or remaining seats.

The published process is to create an EasyConferences account, verify the email, log in through the VLSI-SoC 2026 direct page, and create an order. The organizer lists credit card or bank transfer as payment methods and limits booking updates to the period before online registration closes, subject to availability.

The official registration page gives a separate contact for visa requests. This guide does not generalize visa approval, processing time, entry conditions, or required documents. Current conditions from the organizer and the relevant government owner control actual access.

The 4-day program: separate tutorials day from the 3 conference days

VLSI-SoC 2026 four-day program geometry — Each date keeps the official opening marker and last published block distinct. Source: official page. Figure: VLSI Korea.

Sunday, 2026-10-11, is tutorials day. The official schedule publishes registration at 08:00, morning tutorials beginning at 09:00, and afternoon tutorials beginning at 13:00. Tutorial 1 and Tutorial 2 run in parallel, followed by Tutorial 3 and Tutorial 4 in parallel. The IFIP WG10.5 meeting at 16:30 is marked as a closed session with duration TBA.

Monday, 2026-10-12, begins with registration at 08:00 and the welcome ceremony at 08:30. After the 09:00 academic keynote, RS1 AI/ML Hardware Architectures I and RS6 System Verification, Test & Dependability run in parallel at 10:20. An industrial keynote at 11:50, parallel regular sessions at 13:30, and parallel special sessions at 15:20 follow; the welcome reception runs from 17:30 to 19:00.

Tuesday, 2026-10-13, includes an academic keynote at 09:00, parallel regular sessions at 10:20, an industrial keynote at 11:50, and the AI chip-design panel from 13:30 to 14:15. At 14:15, Sustainable Intelligence at the Edge Part 1 runs in parallel with DfT, Reliability & Functional Safety for Edge AI SoCs. The official program separately blocks poster display and the evening tour/dinner.

Wednesday, 2026-10-14, starts with an academic keynote at 09:00. Digital Design & EDA II runs in parallel with Communications, Sensing & Emerging Technologies at 10:20. An industrial keynote at 11:40 and parallel special sessions at 13:20 follow; the closing ceremony begins at 15:10, and the program states that the conference ends at 16:10.

The calendar's all-day marker and the conference timetable operate at different information levels. The calendar record establishes edition identity, while the official program owns the times needed for travel and session selection. A single saved calendar date cannot resolve parallel-session conflicts.

Program lanes: connect reader jobs to official session IDs

VLSI-SoC 2026 sessions grouped by engineering reader job — An editorial taxonomy connects official session titles to EDA, AI, security, and low-power jobs. Source: official page. Figure: VLSI Korea.

The EDA and verification lane includes Monday RS6 System Verification, Test & Dependability, Monday RS3 Digital Design & EDA I, and Wednesday RS4 Digital Design & EDA II. The program publishes paper titles involving synthesis, optimization, timing, asynchronous design, FPGA work, hardware-software verification, and HDL validation under those sessions.

The AI accelerator and compute-in-memory lane includes Monday RS1 AI/ML Hardware Architectures I, Tuesday RS2 AI/ML Architectures & Computing Paradigms, and Wednesday SS 16 on memristive-based compute-in-memory. This is a VLSI Korea taxonomy that aligns official session and paper titles to reader jobs, not an organizer recommendation.

The security, DfT, and reliability lane crosses Monday RS6, Tuesday RS5 Hardware Security & Testing, Tuesday SS 155 DfT, Reliability & Functional Safety for Edge AI SoCs, and Wednesday SS 16. The same paper is not counted as independent evidence in multiple lanes, and official timetable conflicts remain visible.

The low-power and embedded lane links Monday RS7 Embedded Systems & Low-Power Design, the Tuesday industrial keynote, Tuesday SS 150a, and Wednesday SS 150b. The official program publishes titles involving RISC-V SoCs, SRAM-based in-memory computing, edge intelligence, embedded systems, and memristive platforms, but this guide does not predict performance results.

Academic and industrial keynotes occupy separate plenary blocks. Published titles cover sustainability and security, agentic SoC design, approximate computing for AI accelerators, IP reuse, low-power IC design, and embedded systems. Speaker biographies and titles do not support inventing an unpublished slide, product announcement, or benchmark.

Parallel sessions: preserve every conflicting time block

VLSI-SoC 2026 published parallel session blocks — Official sessions that occur together remain visible instead of hiding timetable conflicts. Source: official page. Figure: VLSI Korea.

RS1 and RS6 run together in the Monday 10:20 block. RS3 and RS7 run in parallel at Monday 13:30, while SS 154 and SS 85 run in parallel at Monday 15:20. Because the official program places different room tracks at the same time, this guide does not imply that one attendee can attend all of them in person.

RS2 and RS5 run in parallel at Tuesday 10:20. SS 150a and SS 155 run in parallel at Tuesday 14:15. On Wednesday, RS4 and RS8 overlap at 10:20, while SS 150b and SS 16 overlap at 13:20.

The official program verifies each block's session title and start time, but the owner packet reviewed for this guide does not contain room names. This guide therefore adds no invented room, internal walking route, minimum transfer minute, or seat-arrival time.

Some poster display and PhD & Student Forum times share coffee-break blocks. The official program states that all 10 posters are displayed simultaneously on Tuesday. That is the schedule's published count, not a guarantee of author attendance or access to an individual poster.

VLSI-SoC 2026 venue and social-program access envelope — Venue identity, social times, and registration inclusion are reconciled across owner pages. Source: official page. Figure: VLSI Korea.

The St. Raphael Resort is the conference venue. The organizer travel page publishes the hotel address and phone, while the venue site confirms the St Raphael Resort & Marina identity and conference facilities. Hotel photographs without an explicit reuse license are not copied into this article; they remain source links only.

The welcome reception is published for 2026-10-12 from 17:30 to 19:00 on the venue hotel grounds, with the organizer noting that the exact location may vary with weather. The registration page includes the welcome reception in full and student access but distinguishes the one-day category by excluding the social event.

The tour and conference dinner are published as an official social program departing from the hotel lobby on 2026-10-13. The technical schedule marks a tour block beginning at 17:00, while the social-program note gives a 17:00 lobby meeting and 17:15 departure. This guide preserves both owner blocks and creates no separate boarding buffer.

The organizer says the tour is weather permitting and that return buses stop at conference hotels. The public page does not establish which hotels qualify, whether an external attendee can make an additional purchase, or how much capacity remains.

Transport: state only the operator chain linked by the organizer

Official transport owner chain from Cyprus airports to the conference venue — Only airport, shuttle, and local-transport owners linked by the organizer are shown. Source: official page. Figure: VLSI Korea.

The organizer travel page identifies Larnaca International Airport and Paphos International Airport as Cyprus gateways and links to the official Hermes Airports site. Hermes Airports is the official operator for Larnaka and Pafos airports. This guide supplies no specific flight, airline, fare, or connection.

For Larnaca Airport to Limassol, the organizer's published chain uses Limassol Airport Express to Saint George Havouzas, followed by an EMEL local bus or taxi. The organizer page states 50 minutes for the shuttle segment, but that is not a traffic or timetable guarantee; the current operator timetable remains the final owner.

From Paphos Airport, the organizer publishes either Limassol Airport Express or a chain using public bus route 613, Intercity Buses, and EMEL. The organizer page states 45 minutes for the shuttle segment. This guide does not calculate successful transfers, waiting time, ticket availability, or operating days.

The organizer also lists private or shared airport transfer through EasyConferences. The registration system may handle accommodation, airport transfers, and car hire, but that fact is not a VLSI Korea recommendation about the price, quality, or availability of any transport option.

For local Limassol transport, the organizer says Bus 30 connects the St. Raphael Resort with the city center and links the operator timetable. Because fares and intervals can change, this article does not freeze older figures from the organizer page and records the operator page as the final pre-departure check.

Connectivity is worth sorting out the same way. A Cyprus data eSIM from Saily can be installed before departure, so there is no need to buy a local SIM or switch on roaming after you land. Purchases through this link may generate a commission.

Official-owner check sequence before departure

Confirm category, registered identity, amount, payment, and availability on the VLSI-SoC registration page and EasyConferences order.
Reconcile the selected day's start times, parallel sessions, tutorials, posters, and social blocks against the official program.
Confirm the address and conference venue identity on the organizer travel page and St. Raphael official site.
Check current operating notices and timetables on Hermes Airports, Limassol Airport Express, EMEL, and Intercity Buses owner pages.
For visa, entry, accessibility, or special access needs, check the current organizer and relevant government-owner conditions.

This sequence creates no new access condition or travel advice. It keeps registration, program, venue, and transport records with their separate owners and provides a final evidence-chain reconciliation. If public information changes, each official owner's latest page takes priority over this article.

Sources

Editorial note: This guide was structured with AI assistance and checked on 2026-08-28 against official owner material for event identity, program, registration, venue, and transport claims. Source snapshots and the fact-check ledger remain in the local package; no private or attendee-only material was used. No subscriber email will be sent.

Preparing your talk: If you are presenting or handling Q&A in English at an international conference, practising spoken English beforehand helps. Preply offers 1-to-1 online English lessons you can tailor to presentation practice. Purchases through this link may generate a commission.

Frequently Asked Questions

When and where is VLSI-SoC 2026 held?

VLSI-SoC 2026 runs from October 11 to 14, 2026, at the St. Raphael Resort, Amathus Avenue 502, 4534 Pyrgos, Limassol, Cyprus. October 11 is tutorials day, and the main conference program runs from October 12 to 14.

What are the late registration dates and the published one-day price?

Late non-author registration is open from August 22 to October 11, 2026. Only late one-day registration is publicly priced, at 300 euros; the official page does not state a late full-registration amount and directs attendees to the registration platform.

What does full registration include?

Full registration includes all sessions, symposium proceedings, the program booklet, coffee breaks, lunches from Sunday through Wednesday, the Monday welcome reception and the Tuesday social event. One-day registration covers the chosen day but excludes the social event.

What proof do student registrants need?

Student registration requires a valid student card. A fee-table note also asks for proof of student status in the form of a student ID or institution letter.

Related reading