What a Logic Synthesis Compile Actually Changes: 5 Circuit States Traced with Yosys and ABC

A logic-synthesis compile is not one translation from RTL to gates. It is a sequence of representation changes: the tool fixes HDL meaning, lowers procedural processes into state and selection logic, restructures arithmetic and Boolean operators, decomposes the result into generic gates, and finally maps that graph into standard cells allowed by a Liberty library. When two compiles diverge, the first useful question is therefore not “Why is the final WNS bad?” It is “At which representation did the two runs first become different?”

This article does not repeat our existing RTL-to-GDSII logic-synthesis introduction. Instead, it sends a 4-bit SystemVerilog teaching design through Yosys 0.67+post and Berkeley ABC, saving JSON, RTLIL, netlist and log artifacts after each major boundary. The objective is not to benchmark commercial synthesis PPA. It is to observe what disappears, what is created, what changes names, and what evidence a Physical Design team needs to receive with the mapped netlist.

VLSI Korea view: Compile is a chain of representation contracts, not a single RTL-to-gate conversion. Each state passes meaning, constraints and proof obligations into the next. Looking only at the final report can hide the first broken contract.

1. Why inspect the inside of compile now?

Public Yosys documentation separates passes that preserve coarse-grain operators from those that lower them to bit-level gates. Combining versioned pass documentation with saved execution artifacts turns that distinction into a debugging observation. A conference-program lead prompted the question; unpublished talk methods and performance results are not evidence for this article.

This is not only a front-end concern. With identical RTL text, a different elaboration parameter, reset interpretation, SDC coverage, dont-use list, library corner, physical guidance file or tool build can produce a different mapped graph. That difference changes placement density, high-fanout topology, buffering freedom, congestion hot spots, path grouping and ECO difficulty. Compile does more than create a P&R input file. It shapes the problem that P&R must solve.

Our probe includes two additions that produce a 5-bit result, an XOR path, a select mux, an active-low asynchronous reset, an enable, a zero detector and a parity reduction. We deliberately added an all-ones mask and a reduction cone with no fanout. That makes constant simplification, dead-code cleanup, process lowering, enable extraction, arithmetic aggregation and technology mapping visible in a small design.

2. State 00, Elaborated: fix design meaning before optimization

After read_verilog -sv and hierarchy -check -top compile_probe, the first snapshot contained 30 wires, 102 wire bits, 1 process and 10 cells. Those cells are not standard cells. They are Yosys internal operators: two $add cells plus compare, mux, reduction and XOR operators. The always block still exists as a process.

Elaboration applies parameters and resolves generates, widths, signedness, hierarchy and the selected top. The same RTL commit can produce a different first state when top parameters, defines, file order, include paths or black-box declarations differ. “We synthesized the same RTL” is not a reproducibility statement unless it includes the top, parameter overrides, defines, ordered source manifest and tool front-end settings.

The practical checks here are straightforward. Does the expected hierarchy exist? Are there unintended latch, undriven-net or multiply-driven-net warnings? Do width extension and sign extension match the design intent? Was a memory recognized in the expected shape? If two runs already have different operator types or bit-width histograms at this snapshot, comparing their final area reports will not identify the cause.

2.1 State 01, Process-lowered: an always block becomes state and muxes

After the proc pass, the process count fell from 1 to 0. An explicit 5-bit $adff state element (1 cell) with asynchronous reset appeared, accompanied by 2 muxes and other operators. The snapshot contained 34 wires, 110 bits and 10 cells. The raw cell count did not change, but the representation changed fundamentally. “Update on the rising edge, reset on the falling reset edge, and hold unless enable is true” became a structural contract made from resettable state and data-selection logic.

A common debugging failure is to compare source lines directly with a deeply mapped state point. Reset-branch priority, incomplete assignment, blocking versus nonblocking assignment, array access and the coding pattern for enables can change inference. If register count is unexpected before retiming or clock gating, inspect the process-lowered state before descending into standard-cell names.

A separate official process example reads RV rather than a constant in its reset branch. The AD input of $aldff exposes that distinction. Asynchronous load and constant reset are different contracts, despite similar names; this reference is not the probe's $adff.

The unit of “one register” also changes across the flow. In this state, $adff is one word-level cell with width 5. In the fine-grain state, it becomes 5 bit-level flip-flops. A report that counts 1 internal word cell and a report that counts 5 library cells can describe the same state capacity. Treating the difference as an optimization regression would be a category error.

2.2 State 02, Coarse-optimized: remove logic while preserving useful structure

We then ran opt_expr, opt_clean, wreduce, peepopt, share, alumacc and opt. The result contained 23 wires, 84 bits, 0 processes and 7 cells. The all-ones mask and the no-fanout reduction cone were already absent from the process-lowered snapshot. Earlier processing, including opt_expr -keepdc within proc, must not be credited solely to coarse optimization. The two additions were represented as two $alu operators rather than immediately decomposed into low-level gates. The enable was combined with the state element as $adffe.

Coarse IR preserves word-level arithmetic and sharing opportunities while removing redundant logic. Passes can combine operators or expand them into primitives, so minimizing cell count across representations is not a meaningful objective.

Exact disagreement: The intuition that cell and wire counts must keep falling as compile progresses is wrong. A change from word-level operators to bit-level gates can multiply the count without changing functionality. Metrics become comparable only inside the same representation, library, constraint set and report definition.

The proof regenerates gold by reading RTL and running proc and opt_clean; gate is the saved coarse snapshot. After equiv_make, the script applies async2sync and opt_clean. In that verification model, equiv_simple -seq 4 proves 27 points and equiv_induct -seq 4 proves 5, yielding 32 proven and 0 unproven. The conversion models asynchronous signals synchronized to the clock and assumes negative hold time: reset deasserted at a clock edge retains the reset value for the next cycle. The proof applies only within this transformed verification model. It does not verify analog reset release, metastability, unrestricted asynchronous timing, full RTL-to-mapped LEC or production signoff.

3. 03 Fine-grain and 04 Library-mapped: generic gates become legal library cells

After techmap, the fine-grain state contained 41 wires, 108 bits and 59 cells: 18 ANDs, 12 ORs, 19 XORs, 4 muxes, 1 inverter and 5 bit-level DFFE cells. That is more than eight times the 7 cells in the coarse state, but the function did not become worse. 5-bit word operations had been expanded into Boolean primitives.

We then loaded the typical NangateOpenCellLibrary Liberty file and ran dfflibmap followed by abc -liberty. dfflibmap maps 5 DFFR_X1 cells, and ABC maps the combinational logic to 48 library cells, giving a final total of 53. ABC alone did not map all 59 cells from the preceding fine-grain snapshot. The mix included 5 DFFR_X1 cells, 5 MUX2_X1 cells, 10 XOR2_X1 cells, 10 XNOR2_X1 cells, plus NAND, NOR, AOI and OAI structures. Yosys reported a total library area of 90.174 and a sequential area of 26.600.

This is the core of technology mapping. A generic Boolean graph offers multiple cuts and structures for the same function. Liberty describes legal cell functions, timing arcs, slew/load tables and area. The mapper selects a legal implementation against its available cost model. This run, however, had no clock period or I/O delay. The statement “the design met timing at area 90.174” would therefore be false. The precise statement is that an unconstrained educational mapping reported 90.174 in the area units of this Liberty file.

Public documentation for Synopsys Design Compiler and Cadence Genus describes physically aware or topographical context, congestion prediction, placement correlation, multi-bit registers, clock gating and datapath optimization. Those descriptions are vendor claims about product capabilities. Our open experiment neither reproduces the same algorithms nor compares QoR. What it does expose is the shared interface: RTL, constraints, libraries and physical context jointly determine the mapped graph.

3.1 Do not confuse an unconstrained compile with a physical-aware compile

The omissions in this probe are deliberate and important. It has no SDC clock, input or output delay, maximum transition, capacitance or fanout rule, and no multi-mode multi-corner scenario. It has no floorplan, macro blockage, placement, routing congestion or extracted RC. The experiment is suitable for observing logical transformations, not for discussing timing closure.

In a timing-driven compile, the same Boolean function may need a different structure for a critical path: a stronger drive cell, buffer tree, replicated driver, alternate mux decomposition or different carry organization. Once physical feedback is included, a logically shallow structure can perform badly because of wire delay or congestion. A slightly larger logical implementation can improve post-placement WNS and routability.

OpenSTA documents inputs including Verilog netlists, Liberty, SDC, SDF and SPEF. The public OpenROAD Flow Scripts platform-bring-up guidance requires not only Liberty but also artifacts such as LEF, GDS and SDC. The message is operational: a synthesis number is not an independent truth. It belongs to a specific analysis view, library, constraint set and physical abstraction. A handoff that sends only a netlist asks the Physical Design team to solve a problem it cannot reproduce.

4. Find the first broken contract, not the last bad metric

First, front-end semantics. Confirm the source commit, top, parameters, defines, includes, black boxes, widths, signs and reset polarity. Compare elaboration warnings and operator/bit-width histograms. If this state differs, do not begin with mapping or timing.

Second, constraint coverage. Confirm every sequential clock, each generated clock's master and division relation, the reference clock for I/O budgets, and the scope of false and multicycle paths. “Unconstrained endpoints 0” is not sufficient. A constraint can exist and still express the wrong design intent.

Third, mapping legality. Compare target and link libraries, corners, operating conditions, dont-use policy, tie, filler and clock-cell policy, plus maximum transition, capacitance and fanout rules. Check for remaining internal cells or black boxes and verify that reset polarity and enable behavior have legal sequential implementations.

Fourth, physical correlation. Record the floorplan version, macro locations, utilization, blockages, routing layers, RC corner, clock assumptions and congestion estimate. If synthesis and P&R reference different physical snapshots, a correlation failure can be mistaken for a tool-quality failure.

Fifth, proof boundary. State exactly which two artifacts formal equivalence compared: RTL versus post-synthesis, pre- versus post-retiming, before versus after scan insertion, or before versus after ECO. Record black-box and initialization assumptions. “LEC passed” is not a description of what was proven.

5. Hand Physical Design a reproducible compile state, not only a netlist

A useful handoff is larger than one Verilog file. The first bundle is identity: RTL commit, ordered source manifest, top, parameter and define values, synthesis script, tool name and build, and run ID. The second is constraints: SDC, scenario manifest, clock table, exception review and unconstrained-path report. The third is technology: Liberty corner and hash, LEF and technology data, dont-use and mapping policies, and the version of physical guidance. The fourth is proof and reports: mapped-netlist hash, area/timing/power reports, warnings and check results, plus the equivalence boundary and proof log.

With that structure, “the tool behaved strangely” becomes a precise diff. Did elaboration produce different operators? Did process lowering produce different state points? Did arithmetic sharing diverge in the coarse state? Was the generic graph identical but library mapping different? Was the netlist identical while a different SDC or RC view changed only the timing report?

The Physical Design approval question changes as well. Instead of asking only whether the netlist arrived, ask whether the team can reopen the exact constraints, libraries and physical context that created it. Ask which artifact explains decisions on major path groups and high-fanout nets. Ask what timing view and equivalence boundary will be used after P&R performs remapping, resizing, buffering or cloning.

6. What this experiment says, and what it does not

The experiment supports observable IR states, representation-specific cell counts, and artifact provenance for debugging and handoff.

It does not compare Yosys/ABC with Synopsys Design Compiler, Cadence Genus or any other commercial tool. Nangate45 typical is an open educational library, not a production PDK. Without timing constraints, placement, RC or power activity, the run cannot establish silicon PPA or correlation. A 32-point proof on a 4-bit block does not represent SoC-scale LEC difficulty.

The next useful experiment is to add one contract at a time. Add a clock period and I/O delays and observe the mapped cell mix. Add transition and fanout rules and trace buffering or replication. Place the block in OpenROAD, estimate RC and measure the gap between synthesis and post-place timing. Finally, add a transform that changes state correspondence, such as retiming or clock gating, and redefine the LEC boundary.

What Korean RTL and PD teams can change first

The RTL owner finds the first structural divergence; the PD owner decides whether the handoff is reproducible. This separation is useful when Korean fabless and design-service teams use different tool builds or library views. Use public libraries for the teaching probe and keep customer RTL, foundry PDKs and internal reports out of public examples. Base delivery decisions on reproducibility within the same representation and an actual constrained timing view, rather than a raw cell-count reduction. This is a collaboration proposal derived from the experiment, not an observation about adoption by Korean companies.

Read the meaning of each cell name during handoff review. The official counter example uses $sdffe for synchronous reset and enable. Its statistics are not a direct comparison with our asynchronous-reset circuit; the reference helps check which control semantics each state element preserves.

The thesis has failure conditions. First, if identical manifests do not produce a stable first divergence, pass snapshots alone have limited diagnostic value. Second, if a difference arises only inside final physical optimization and the flow exposes no intermediate state, these five states are insufficient. Add vendor-supported database checkpoints and post-placement analysis in that case.

The following are experimental review dates. On 2026-12-07, check repeatability with source, build and library fixed. On 2027-03-07, separate mapping changes from timing changes after adding public clock and I/O constraints plus placement RC. On 2027-09-07, recheck whether a proof with an added state transformation matches the actual release boundary. These are neither product-launch forecasts nor promises of completed runs. Without the corresponding artifacts, the result remains unknown.

Practitioner summary: When a compile changes, do not start with final WNS. Walk Elaborated → Process-lowered → Coarse → Fine-grain → Mapped, find the first diff, and identify whether it entered through RTL meaning, constraints, libraries or physical context.

Public evidence and reproduction boundary

We cross-checked the mechanism and interfaces with Yosys Synthesis in detail, its current technology-mapping pass documentation, the official Berkeley ABC project description, OpenSTA and the OpenROAD Flow Scripts user guide. We used public Synopsys Design Compiler and Cadence Genus documents only to describe vendor-stated commercial-flow boundaries. The DAC 2026 program served only as a discovery source for current research questions.

The experiment ran on 2026-09-02 KST with Yosys 0.67+post and NangateOpenCellLibrary_typical.lib pinned to ORFS commit 8c0616910615e843780ba527526f2b83a564ba70. The library SHA-256 is 8d540a4d4cf6d09d27c87ad067857a9c0c2eeb023ab7a56e058cd3113db4e9b1. Stage statistics, stage JSON, mapped Verilog, proof logs and visuals are preserved in the same local review package.

Source figure license and attribution

YosysHQ documentation, copyright 2025 YosysHQ GmbH. Repository permission notice reproduced below. Diagrams preserve source geometry; rasterization and watermark added by VLSI Korea.

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Copyright (C) 2012 - 2026 Claire Xenia Wolf <[email protected]>

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Editorial transparency: AI assisted public-document research, draft organization and visual production. The experiment commands ran locally, and the numeric results and proof log were checked against the saved artifacts. No unpublished conference content was generated. VLSI Korea retains editorial responsibility.