industry-research

DAC 2026 Agentic EDA: What 222 Papers Say About Trustworthy Closure

DAC 2026 maps 222 EDA papers. Production agentic EDA depends on constraint-preserving closure and auditable failure evidence.

Chase Na 나경채

25 8월 2026, 09:35 KST Updated 22 10월 2026, 13:49 KST · 7 min read ·

AI-generated conceptual image - VLSI Korea

Executive summary

Conclusion: Agentic EDA needs a constraint-preserving closure loop that lets deterministic tool results choose the next experiment, not a model that emits RTL once.
Scope: Of 545 DAC 2026 research-paper titles, 222 map to EDA workflows: 99 verification, formal and test; 41 analog, RF and circuit; 33 RTL, HLS and logic; 29 physical design and signoff; 15 other EDA; and five cross-cutting AI-for-EDA titles.
Decision: Verification leaders should demand denominators, oracles and reproducibility, then begin with a narrow, auditable regression or debug pilot.
Caution: The 544 accepted IDs and 545 PDF titles remain an unresolved source discrepancy, not an acceptance statistic.

Horizontal bar chart classifying 222 DAC 2026 design-automation papers by engineering cluster — VLSI Korea classification of research-paper titles in the official DAC 2026 program PDF. This is not an official DAC track statistic.

VLSI Korea view: The 2026 competition is moving from code generation to evidence-preserving closure. Tool results, not model confidence, should change engineering state, and every constraint change and human edit needs an audit trail.

DAC ran in Long Beach from July 26 to 29, 2026. Its official program contains 175 timed blocks and 72 Research Manuscript sessions. We retained every one of the 545 paper titles in a public ledger, then reduced the 222 design-automation titles into five core engineering clusters plus a cross-cutting AI-for-EDA set. Where only a title was public, we did not infer results beyond that title. Mechanism analysis uses session descriptions and dated primary sources.

The Korean original uses the same evidence ledger, numbers and visuals. We did not bypass the paid proceedings or reproduce paper text. This is a sector-level synthesis of the public program, not a substitute for the papers.

Use the DAC 2026 545-paper topic map for edition-wide composition and the DAC 2026 company-material index for the public vendor evidence. This article does not recycle their count paragraphs; it asks the separate engineering question of how an agentic loop earns production trust.

Trustworthy agentic EDA loop from intent and constraints through planning, execution, measurement, diagnosis and closure — VLSI Korea mechanism figure. The model proposes actions; lint, simulation, formal, STA and signoff tools provide engineering truth.

1. Verification, formal and test: 99 papers point to the oracle

The largest cluster contains 99 titles spanning natural-language test plans, assertion generation, coverage closure, waveform debug, root-cause analysis, formal properties and security verification. Verification is attractive for agents because pass or fail, counterexamples, coverage and waveforms provide an external oracle. An agent can act, measure the result and update its plan.

Specification interpretation and microarchitecture choices are less forgiving. RTL may compile and pass curated tests while omitting requirements or mishandling reset, CDC, X propagation or liveness. A production agent therefore cannot jump directly from a prompt to RTL. It must structure intent, generate tests and properties independently, and store simulation and formal evidence together.

Synopsys' official DAC material describes design and verification agent teams operating tool-grounded iterative loops. Cadence says ChipStack iterates from specification understanding through simulation and formal analysis and claims over 40x faster RTL validation in its named deployment context. That number is a vendor claim bound to Cadence's task and baseline. It is not a cross-vendor ranking without the same design, constraints, tool versions, compute budget and human-touch policy.

Five-level evidence ladder for agentic EDA claims from narrative demo to independent reproduction — VLSI Korea framework. The ladder measures depth of public evidence, not overall product quality.

2. RTL, HLS and logic: 33 papers move the model into the search loop

The 33-title RTL, HLS and logic cluster includes Verilog generation, reinforcement learning with testbench feedback, HLS design-space exploration, datapath gating, SAT sweeping and multi-die FPGA floorplanning. The important shift is from using a language model as a code writer to using it as a search policy. The agent proposes candidates, reads synthesis, equivalence, timing and power results, and selects the next move.

This also creates reward-hacking risk. A candidate can improve a benchmark by relaxing a latency constraint, deleting unsupported behavior or exploiting gaps in the tests. Golden behavior, clock and reset protocols, exception lists, SDC and formal assumptions must remain fixed. Smaller logic is not an improvement unless function and operating envelope are unchanged.

The most useful unit of evaluation is a closed task. Reproduce a failing regression, identify the root cause, create a patch, and prove that the full regression, lint, formal checks and QoR did not deteriorate. Counting only passed tests misses deleted tests and overfitting. The denominator should include total issues, first-pass success, escalation rate, false fixes and rollback.

Coupled closure loop connecting RTL, placement, routing, timing, power, thermal, formal and simulation — VLSI Korea mechanism figure. A local optimum does not guarantee whole-flow closure.

3. Physical design and signoff: 29 papers confront coupled objectives

We classified 29 titles in placement, routing, timing, IR drop, thermal, clock and power optimization. The count is smaller than verification, but production risk is higher. A local backend win often becomes downstream debt: a placement that reduces congestion can increase wirelength and skew, a setup fix can damage hold and dynamic power, and an IR improvement can move a thermal hotspot.

An agent has to compress global state without losing modes and corners. Rewarding one WNS, TNS or congestion metric hides path groups, SI, EM, IR, temperature and DRC coupling. A safer role is to propose the next ECO or tool setting, summarize multi-objective deltas, and manage reversible experiments.

Synopsys' public multiphysics direction and Cadence's InnoStack and AgentStack target this coupling. Signoff accuracy, however, is independent of a marketing autonomy level. If the PDK, extraction deck, libraries, parasitic corners, activity and thermal boundary conditions are not fixed, a speedup comparison is not defined.

4. Analog, RF and circuit automation: 41 papers expose sparse oracles

Risk register mapping four agentic EDA actions to hidden failures and deterministic release gates — VLSI Korea framework: every agent action needs a downstream deterministic gate; this is not a product ranking.

The 41-title analog, RF and circuit cluster shows that this is no longer a small niche. Schematic synthesis, sizing, surrogate models, SPICE acceleration, migration and layout generation are meeting agentic workflows. Analog oracles are more expensive and discontinuous than digital ones. Convergence failures, multiple operating points, PVT corners, mismatch and layout-dependent effects create sparse feedback.

A realistic system therefore combines topology libraries, constraint graphs, simulator-in-the-loop search and uncertainty estimates. It should report how many pre-layout candidates fail after extraction, how many restarts are required, corner yield and human intervention. Passing one typical point is a demonstration, not expert replacement.

Korean teams can start with mature-node PMIC, display, sensor-interface or memory-peripheral blocks that reuse topologies and characterization assets. The decision metric should be post-layout pass rate, review findings, re-spin risk and knowledge reuse rather than schematic-entry time.

5. A 90-day pilot should be narrow and reproducible

A first pilot can target block-level regression triage, assertion candidates, lint or CDC waiver review, or constrained ECO suggestions. Use read-only tool access and an isolated sandbox before connecting production databases. Define which files, constraints and job budgets the agent may change.

Required benchmark record fields for design, ground truth, constraints, tools, agent and outcomes — VLSI Korea reproducibility checklist. Task, denominator, oracle and unchanged constraints are the minimum disclosure unit.

The baseline must use the same engineer-facing tools and compute budget. Measure false diagnosis, invalid patches, regression escapes, coverage and QoR deltas, escalation and rollback in addition to time saved. Even if internal results cannot be published, the internal approval package needs those denominators.

Thesis breaker: If success collapses on a new design or tool version, humans effectively rewrite prompts and constraints, or full regression and signoff erase the time saving, agentic closure is not yet production-ready. The next proof point is a reproducible task definition and failure distribution, not another customer logo.

6. Method and complete coverage ledger

We parsed 175 timed blocks in the official July 22 DAC PDF and extracted 545 bullet titles from 72 Research Manuscript sessions. A deterministic classifier used the session topic and title keywords; boundary cases were reviewed. These are VLSI Korea categories, not official DAC sector counts. Each title is assigned to one primary bottleneck even when the work spans several.

We preserved the mismatch between 544 IDs on the accepted-paper page and 545 titles in the program PDF. We did not remove an arbitrary title or use the difference to compute acceptance rates.

Ninety-day agentic EDA pilot sequence from frozen baseline to shadow mode controlled writes and release review — VLSI Korea deployment framework: advance only when the evidence transfers to a new design under unchanged constraints.

Download the filtered 222-title EDA, verification and closure ledger · Download the complete 545-title DAC research ledger

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Sources

Editorial note: This article structures public conference programs and primary company sources, uses AI assistance for drafting, and applies VLSI Korea evidence, visual, and release gates. A program listing or vendor claim is not treated as independent proof of measured performance or production readiness. Report corrections to [email protected]. Download the complete DAC paper-title ledger as CSV.

Disclosure

This article is provided for informational purposes only and does not constitute a recommendation to buy or sell any security. Figures and factual statements are based on publicly available sources, including company filings, news reports, and market research, and may contain errors in the source material or in the preparation of this article. The author is employed by Synopsys, and VLSI Korea is operated independently of the employer. All investment decisions and their outcomes are the reader's responsibility.