VLSI KoreaDaily Silicon: SK hynix CPO and HBM: $97.94B in AI Chip Orders
A practicing semiconductor engineer's daily read on global silicon news - SK hynix CPO and HBM: $97.94B in AI Chip Orders
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A practicing semiconductor engineer's daily read on global silicon news:
SK hynix's CPO paper moves the bandwidth constraint beyond HBM packages to rack and pod links, while Taiwan's $97.94B July export orders, up 61.9%, show AI demand could tighten package and interconnect scheduling first.
Chase's Take - I watch CPO optical-engine attach loss, thermal budget, and optical I/O test coverage before HBM stack supply volume. Even if demand metrics rise quickly, package teams will not deliver rack-level bandwidth unless connector, substrate, and laser-coupling qualification close in parallel.
The next check is when PDK, BER, thermal-cycle criteria, and module-level yield are disclosed for CPO deployed on memory links.
1. SK hynix CPO Roadmap: The Rack and Pod Bottleneck After HBM
TL;DR - SK hynix's CPO roadmap defines the next bottleneck beyond the HBM stack as the rack and pod optical link, extending AI-chip design scope beyond the package.
Source: SK hynix - SK hynix CPO Roadmap: The Rack and Pod Bottleneck After HBM
2. Taiwan's $97.94B July Export Orders Pull the Front-End Supply Chain
TL;DR - Taiwan's July export orders hit a record $97.94B, up 61.9% year over year, providing a primary-data signal that AI hardware order flow remains strong.
3. Waymo's 5nm ASIC: A Look Under Our Trunk Compute
TL;DR - Waymo disclosed a 5nm custom ASIC and more than 1,000 TOPS of ML processing, showing that vehicle-AI bottlenecks sit in the sensor data path and deterministic latency, not a single accelerator.
Source: Waymo - Waymo's 5nm ASIC: A Look Under Our Trunk Compute
4. CXMT Planned to Use Samsung IP, Court Hears: DRAM Testimony
TL;DR - Court testimony in the Samsung process-information case alleges unauthorized acquisition of a 600-step PRP, but the legal judgment on that testimony and product-specific liability for CXMT remain unresolved.
Source: Tom's Hardware - CXMT Planned to Use Samsung IP, Court Hears: DRAM Testimony
What to Watch Next
- CPO memory-link PDK, BER, thermal-cycle, and optical I/O test criteria
These measurements decide whether a paper architecture clears module qualification and yield gates. - Taiwan's August export orders and substrate/OSAT utilization metrics
They show whether July's order growth converts into actual wafer starts and package output. - Waymo custom ASIC sensor-fusion latency and thermal-envelope disclosures
This is the next data needed to judge whether more than 1,000 TOPS translates into vehicle-level deterministic response. - Follow-on court rulings in the Samsung process-information case
Separating court testimony from final legal findings avoids overstating DRAM process-IP risk.
Signal Radar - More Headlines
- Cerebras and Callosum Announce European Agentic-Inference Partnership (Cerebras)
- Hybrid-Bonding Challenges in Advanced Packaging for Photonics (NHanced Semiconductors)
- 650W Continuous-Power Resistor Announced (Vishay)
- U.S. ITC Maintains Antidumping and Countervailing Duties on Silicon Metal From Four Countries (U.S. International Trade Commission)
- Custom HBM Makes Design Teams and Tool Capacity Separate Constraints (Semiconductor Engineering)
- Managing CTE and Electromigration Together in Interposer Design (Semiconductor Engineering)
- CFET Connection Research Exposes Interconnect Challenges in 3D Logic (Semiconductor Engineering)
- Three Design Imperatives for Energy-Efficient AI Computing (SEMI)
Further Reading on VLSI Korea
- What Is a Post-CMP Cleaner? The Defect Contract That Closes Particle Removal and Metal Corrosion Together
Useful deeper background for today's brief. - Weekly Silicon: AI Capex Is Validated in Power, Substrates, and WFE
Frames the supply-chain checks implied by today's order signal.
Frequently Asked Questions
What does SK hynix's CPO roadmap identify as the next bottleneck?
The CPO roadmap defines the next bottleneck beyond the HBM stack as the rack and pod optical link. That extends AI-chip design scope beyond the package.
How large were Taiwan's July export orders?
Taiwan's July export orders hit a record $97.94 billion, up 61.9% year over year. The orders are a primary-data signal that AI hardware order flow remains strong.
What did Waymo disclose about its ASIC?
Waymo disclosed a 5nm custom ASIC and more than 1,000 TOPS of ML processing. Vehicle-AI bottlenecks sit in the sensor data path and deterministic latency.
What was alleged in the Samsung process-information case?
Court testimony alleges unauthorized acquisition of a 600-step PRP. The legal judgment on that testimony and product-specific liability for CXMT remain unresolved.
Related reading
- Daily Silicon: HBM, ASIC, CPO All Surging — Memory Cycle Extends…
- Daily Silicon: Samsung, SK hynix: KRW 43.2T HBM, DRAM Facility Spend
- Daily Silicon: DRAM Margins Top HBM, Korea April Chip Exports Surge 174%
- Daily Silicon: AI Breaks 40-Year WSTS Record; HBM Crunch Spills Mainstream
- Daily Silicon: AMAT WFE Guide to 30%+, Foxconn AI Server Surge, Hynix…
