Ascend 950 In-House HBM: 5 Facts on the DeepSeek 160,000-Chip Bet and the Memory Bottleneck (HBM·SuperPoD)

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The battle for Ascend 950 will not be decided by compute but by in-house HBM bandwidth — and the Huawei–DeepSeek co-design is an attempt to break that bottleneck with scale.

30-second summary

• Conclusion first: Huawei announced at Huawei Connect in September 2025 that Ascend 950PR would arrive in Q1 2026 and Ascend 950DT in Q4 2026, on an annual generation cadence.
• Key numbers: the 950PR was announced with self-developed HBM HiBL 1.0 at 128GB and 1.6 TB/s, but the Atlas 350 shipping card reported on March 20, 2026 came in at 112GB and 1.4 TB/s. The gap between roadmap and shipped specs is the first verification point.
• DeepSeek announced via its official WeChat on September 30, 2026 that it had open-sourced an Ascend programming stack including TileLang, alongside a joint "supernode" solution linking 128 Ascend 950 chips.
• Scale: a September 4, 2026 report described DeepSeek planning a roughly 1GW data center in Ulanqab, Inner Mongolia built around 160,000 or more Ascend chips. This is a report, not a confirmed company announcement.
• Own calculation: at 144GB per 950DT chip, a 160,000-chip site corresponds to 23.0PB of total memory capacity (own calculation).

Background

The previous generation, Ascend 910C, entered mass production in Q1 2025 with roughly 800 TFLOPS of FP16, 3.2 TB/s of memory bandwidth, and 128GB of capacity — using purchased HBM. The biggest change in the 950 generation is not the compute core but the memory supply itself. By co-designing self-developed HBM — branded HiBL 1.0 and HiZQ 2.0 — with the logic die, Huawei is moving memory procurement from external supply chains onto its own roadmap.

Export controls sit behind this shift. The December 2024 BIS HBM rule already restricts advanced HBM exports to China, so Samsung Electronics and SK hynix cannot sell HBM to Huawei. An Ascend ramp therefore does not directly take Korean HBM orders. The real question is second-order: if logic, memory, and software all mature inside China as one self-supply stack, one of the largest future HBM demand pools could harden outside the addressable market — and as a competing ecosystem standard.

NVIDIA CEO Jensen Huang said in 2026 public statements that US export restrictions pushed NVIDIA's share of China's advanced AI chip market from about 95% to effectively zero, and that H200 sales to China were under 1% of data-center revenue in the quarter ended July 26, 2026. The central question is how fast — and how far — the Huawei–DeepSeek combination can fill that vacuum.

The software moves in the same direction. TileLang, DeepGEMM, DeepEP, FlashMLA, TileKernels, and DeepSelect — open-sourced by DeepSeek — are mapped one-to-one to their NVIDIA-stack counterparts, and DeepSeek positions TileLang as simpler to program than CUDA. The stated goal is an independent, self-controlled GPU software ecosystem.

Deep Dive

1. An annual cadence split into two tracks — 950PR for prefill, 950DT for decode and training

The conclusion: Huawei did not design one chip but two memory variants tuned for different workloads. Under the roadmap presented by rotating chairman Eric Xu at Huawei Connect in September 2025, Ascend 950PR was slated for Q1 2026 with 1 PFLOPS of FP8, 2 PFLOPS of FP4, 2 TB/s of interconnect, and self-developed HBM HiBL 1.0 at 128GB and 1.6 TB/s, targeting prefill plus recommendation inference. Ascend 950DT was slated for Q4 2026 with 144GB of HiZQ 2.0 at 4.0 TB/s, targeting decode and training. The same announcement placed Ascend 960 in Q4 2027 with 288GB and 9.6 TB/s at roughly twice the compute of the 950, and Ascend 970 in Q4 2028 (roadmap figures, per Huawei's announcement).

2. The Atlas 350 shipping card versus the roadmap — Huawei claims must be read separately from the verification points

The conclusion: the shipped product was reported below the roadmap figures, and every performance comparison must be read as a Huawei claim. At the Huawei China Partner Conference on March 20, 2026, Ascend business head Zhang Dixuan unveiled the Atlas 350, a shipping card based on Ascend 950PR, reported at 1.56 PFLOPS of FP4, 112GB of in-house HBM, 1.4 TB/s of memory bandwidth, and 600W. Huawei claims this card delivers 2.8x the FP4 compute of NVIDIA's H20, 1.16x its HBM capacity, and up to 60% faster multimodal generation speed. These are vendor claims, not independent benchmarks. The gap between the September 2025 roadmap (128GB, 1.6 TB/s) and the March 2026 shipping card (112GB, 1.4 TB/s) is not an error to hide — it is the verification point, and the question is whether the gap closes on the DT variant.

3. The first in-house HBM generation was slower than purchased HBM — bandwidth traded for supply security

The conclusion: the first generation of self-developed HBM steps back in bandwidth, and the roadmap only closes that gap at HiZQ 2.0. The bandwidth ladder, worked out as an own calculation anchored to announcement dates, reads as follows. The Ascend 910C sat at 3.2 TB/s (Q1 2025), the shipped 950PR at 1.4 TB/s (reported March 20, 2026; HiBL 1.0), the 950DT at 4.0 TB/s (planned Q4 2026; HiZQ 2.0), and the 960 roadmap at 9.6 TB/s (Q4 2027). For reference, NVIDIA's public specifications put the H100 at 3.35 TB/s and the B200 at 8.0 TB/s. The shipped 950PR's compute-to-bandwidth structure — 1.56 PFLOPS of FP4 against 1.4 TB/s (own calculation) — points to the same conclusion. Prefill is bandwidth-hungry, so the PR's memory system is itself the constraint; that is exactly why the DT variant exists. In short, the first in-house HBM generation bought supply control and paid for it in bandwidth.

4. DeepSeek's TileLang open source and the 128-chip supernode — the software moved inside chip design

The conclusion: DeepSeek stopped being just a customer and became a co-designer, open-sourcing the programming stack and the supernode architecture together. In its official WeChat announcement on September 30, 2026, DeepSeek open-sourced TileLang (a high-level language and compiler), DeepGEMM, DeepEP, FlashMLA, TileKernels, and DeepSelect, mapped one-to-one to its NVIDIA-stack versions. In the same announcement, with full support from Huawei, the two companies presented a joint "supernode" solution linking 128 Ascend 950 chips and optimizing compute and communication together. Reports from February through April 2026 describe DeepSeek giving Huawei early access to V4 ahead of US suppliers, the V4 preview adapted for Huawei chips, Huawei stating its chips were used in part of V4 training, and DeepSeek V4-Flash optimized for Huawei chips. Each of these items should be read as a dated report.

5. The 160,000-chip deployment report and the 10,000-chip-plus pretraining plan — winning on aggregate, not per chip

The conclusion: Huawei's answer is not per-chip parity but scale-out through SuperPoD and SuperCluster, with DeepSeek reported as the anchor demand. In Huawei's September 2025 announcement, the Atlas 950 SuperPoD binds 8,192 Ascend NPUs into one logical unit in Q4 2026, and the Atlas 960 SuperPoD scales to 15,488 NPUs in Q4 2027. SuperCluster scale was announced at 500,000-plus chips for the 950 generation and 1,000,000-plus for the 960 generation. A September 4, 2026 report described DeepSeek planning a roughly 1GW data center in Ulanqab, Inner Mongolia built around 160,000 or more Ascend chips, with those chips serving inference workloads there. An October 19, 2026 report described Huawei engineers embedded at DeepSeek offices folding training requirements into next-generation chip design, DeepSeek planning to start pretraining on Ascend 950DT by the end of 2026, a full run possibly needing more than 10,000 chips running for weeks, and Huawei expected to allocate most Ascend 960DT supply to DeepSeek with deliveries from Q1 2027. All of these are reports, not confirmed announcements. Converted as an own calculation: at 144GB per 950DT chip, a 128-chip supernode holds 18.4TB, a 10,000-chip pretraining cluster holds 1.44PB of capacity with 40 PB/s of aggregate memory bandwidth (at 4.0 TB/s per chip), and a 160,000-chip site holds 23.0PB. Independent third-party estimates put NVIDIA's B300 raw compute at roughly 7x a single Ascend 950 chip — an estimate — so the per-chip gap remains large even as the strategy moves the contest to system scale.

Chase's Take

The bottleneck moved. At FP4 and FP8, logic dies are close to good enough for inference; the binding constraints are now memory bandwidth per chip, training-software maturity at 10,000-chip scale, and volume. From an STA/EDA practitioner's standpoint, the chip itself is rarely what fails first — it is the memory and interconnect around the chip, and whether training stays stable for weeks rather than days at that scale. I would put less weight on the headline compute numbers and more on the week-three stability logs, which are the ones we do not get to see.

SuperPoD is a systems trade: accept the per-chip gap and win on aggregate through interconnect plus software co-designed with the anchor customer. Having DeepSeek's engineering requirements flow directly into Huawei's chip design mirrors the hyperscaler-ASIC co-design pattern. When demand defines the specification, roadmap waste shrinks — but so does the insurance policy, because the silicon gets tuned to one customer's workloads.

Readers can compress the verification into four questions. First, does the 950DT actually ship in Q4 2026 at 4.0 TB/s in product, not on a roadmap? Second, does the reported end-of-2026 pretraining run complete and get disclosed? Third, does TileLang hold training stability past 10,000 chips? Fourth, does the 112GB-versus-128GB shipping-card gap close on the DT variant?

Implications

For investors, this is not a story about Korean HBM revenue being taken away today. Since the December 2024 rule, Samsung Electronics and SK hynix have been unable to sell advanced HBM to Huawei anyway. The implication is the long-term addressable market shrinking: if a self-supply stack of Ascend logic, HiBL/HiZQ memory, and domestic DRAM matures inside China, one of the largest future demand pools hardens into a standard that outside suppliers cannot reach. A TileLang-centered software ecosystem and a SuperPoD interconnect standard would accelerate that lock-in.

For management, the CXMT variable belongs in the same frame. If Huawei's in-house HBM covers the premium tier but domestic memory volume does not follow, a 160,000-chip deployment stays a paper plan. If volume does follow, the discussion moves from single-chip performance to data-center total cost of ownership, power, and software switching costs.

For NVIDIA, the share numbers already tell the story: per Jensen Huang's 2026 statements, its position in China's advanced market is effectively gone. The contest is shifting inward — to who becomes the standard inside China. If the Huawei–DeepSeek combination closes the training loop stably, the "inference-only alternative" label no longer holds.

FAQ

Q: What is the difference between Ascend 950PR and 950DT? A: Under Huawei's September 2025 roadmap, the 950PR was slated for Q1 2026 with 128GB of HiBL 1.0 at 1.6 TB/s for prefill and recommendation inference, while the 950DT was slated for Q4 2026 with 144GB of HiZQ 2.0 at 4.0 TB/s for decode and training. The Atlas 350 card shipped March 20, 2026 was reported at 112GB and 1.4 TB/s, so the roadmap-versus-shipped spec gap must be tracked.

Q: Is Huawei's 2.8x H20 performance claim verified? A: No. The 2.8x FP4 compute, 1.16x HBM capacity, and up to 60% faster multimodal generation speed announced March 20, 2026 are Huawei claims, not independently benchmarked figures. Every performance comparison in this article is labeled as a Huawei claim.

Q: Is the DeepSeek 160,000-chip deployment confirmed? A: It is not a confirmed announcement. A September 4, 2026 report described a roughly 1GW plan in Ulanqab, Inner Mongolia around 160,000-plus Ascend chips, and an October 19, 2026 report described DeepSeek planning to start pretraining on Ascend 950DT by end of 2026. As an own calculation, 160,000 950DT chips correspond to 23.0PB of memory capacity.

Q: Does the Ascend ramp hurt Samsung Electronics and SK hynix directly? A: Not in direct orders. The December 2024 BIS HBM rule already bars advanced HBM exports to China, so neither company can sell HBM to Huawei. The risk is second-order: a maturing Chinese self-supply stack hardens a future HBM demand pool outside the addressable market, and CXMT's HBM progress is the volume complement to watch.

Figures in this article rest on Huawei announcements, the DeepSeek announcement, NVIDIA statements, and date-stamped reports as marked; Huawei performance comparisons are Huawei claims, deployment and pretraining items are reports, and converted figures are own calculations.

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