English - VLSI Korea (Page 3)

English

[VLSI CAD] kbdd - MiniSAT - Espresso - SIS?

When you take an EDA or VLSI CAD class, all of a sudden these tools pop up: * kbdd * MiniSAT * Espresso * SIS At first, they all seem similar: "Isn't this all about logic expressions?" "Do we ever use this in practice?" The bottom line is

English

About Semiconductor Aging - BTI/HCI, Aging SPICE Simulation

Semiconductors age too Today's Semiconductor devices undergo a kind of "aging" phenomenon where their performance slowly degrades over time. Just as mechanical parts wear out over time, MOSFET transistors change their electrical characteristics over long periods of operation, affecting the behavior of the circuit. This phenomenon

English

FPGA vs ASIC: Internal Structure, Differences, and the Future of the Industry

Let's take a deep dive into the inner workings of FPGAs and ASICs and explore the pros, cons, and business implications of both technologies. 1. There are tons of semiconductor chips in our everyday lives, including smartphones, computers, and automotive electronics, but few of us really know the

English

Setup Time and Hold Time - Mastering the Fundamentals of VLSI Timing

Setup Time and Hold Time are two of the most important timing constraints in digital circuits: * Setup Time is the time that data must reliably arrive before the clock edge, and * Hold Time is the time that data must be held after the clock edge. If these two conditions are

English

[VLSI CAD] MiniSAT?

The Satisfiability (SAT) problem is summarized by the following question: Can the variables be set to True / False such that the given Boolean formula is True? For example, given the formula f(x,y,z)=(x || y) & (!x || z), * Finding out how to assign True/False to x, y,

English

What is Unate / Non-unate Cell in Static Timing Analysis?

When you study digital circuit design, you come across unate / non-unate cell, and at first you think, "What's the point?" Unateness is a criterion for STAs to "safely and monotonically define the worst case with simple rules". This is to reduce performance (runtime) and

English

Privacy Policy

Last updated: March 2, 2026 VLSI Korea ("we," "us," or "our") operates the website https://www.vlsi.kr (the "Site"). This Privacy Policy explains how we collect, use, and protect your information when you visit our Site. By using this Site, you

English

Semiconductor design employment and exit strategies

학부생부터 3년차까지, the most frequently asked questions We've compiled a list of the most common job and career questions we've gotten while running VLSI Korea. I write as honestly as possible about the things that professors don't teach you: I apologize in advance. I&

English

How will engineers survive in the age of AI?

My Honest Thoughts I've noticed something odd about LinkedIn job postings lately: Companies are asking for much higher specs than they used to, and yet very few entry-level positions are open. Most of the jobs are for contracting departments with university-industry connections, and the few openings that remain

English

Orbital Data Center (ODC) Technical Report

1. AI requires data centers. 2. Data centers are large and consume significant energy. 3. Cooling systems to reduce heat generation are also necessary. → Cost issues arise. How can we receive more energy in a larger space while consuming less energy? The Orbital Data Center (ODC) is an attempt to

English

[VLSI CAD] Expressed in EDA

What is Espresso? A classic and standard approach that minimizes the number of AND/OR terms while preserving the functionality of the logical expression. Espresso is a Boolean logic minimization algorithm and tool. 1. The Problem Espresso Solves The following two logical expressions perform exactly the same function. f = a

English

[VLSI CAD] Why Two-Level Logic Minimization is Challenging

TL;DR * To solve Two-Level Logic Minimization "exactly," you end up following the Quine–McCluskey (QM) flow. * The bottleneck in QM is the covering (minimum column cover) stage. * Covering is NP-complete, so the "optimal solution" becomes a proof problem rather than a value. * SAT is hardly