korean
Glitch-Free Clock MUX란?
반도체 Tape-out 후 가장 괴로운 버그 중 하나는 이런 형태다. Function simulation도 완벽 , Silicon Bring-up에서도 대부분 정상, 그런데 “가끔” 비정상 동작을 한다. 교수님 앞에서 재현하려고 하면, 또 잘 동작한다.... 재현성이 낮아...
pillar
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What is 'Clock mesh' in Physical Design?
In digital semiconductors, the most critical signal is the clock . The delay from the clock source to the clock pin of a sequential cell is called ...
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Memory Hierarchy & Memory Wall
Key Takeaway: From 1947’s magnetic core memory to the forthcoming HBM4 and compute-in-memory architectures, advances in semiconductor memory have...
![[STA] Synchronous Clocks vs. Asynchronous Clocks](https://images.unsplash.com/photo-1533749047139-189de3cf06d3?crop=entropy&cs=tinysrgb&fit=max&fm=jpg&ixid=M3wxMTc3M3wwfDF8c2VhcmNofDF8fGNsb2NrfGVufDB8fHx8MTc1NTQzMzg1OHww&ixlib=rb-4.1.0&q=80&w=600)
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[STA] Synchronous Clocks vs. Asynchronous Clocks
In the world of digital design, you often hear the terms synchronous clock and asynchronous clock . While simple designs with a single module might use...
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What is Physical Design Rule Checking (Physical DRC)?
Physical Design Rule Checking (DRC) is the cornerstone of semiconductor physical verification, ensuring that an integrated circuit’s layout adheres to the...
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Why is Interconnect Delay Still Large with Advanced Process Nodes?
The continuous scaling of semiconductor process nodes improves transistor density, but it disproportionately amplifies interconnect parasitics ,...
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What is Library Characterization? feat: SPICE, and Static Timing Analysis (STA)
Overview of SPICE and STA In modern high-density VLSI design, it's crucial to ensure that an integrated circuit (IC) operates correctly and reliably at its...
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What is SPEF (Standard Parasitic Exchange Format)?
In the field of Very Large Scale Integration (VLSI) design, a finished semiconductor chip's performance is not only determined by its logical...
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What is MPW (Multi-Project Wafer)?
Multi-Project Wafer (MPW) is a service that allows various semiconductor designs to be fabricated on a single wafer. Think of it like a "variety...
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SDC: Why use 60% IO Delay for set_input_delay and set_output_delay?
Chip design, particularly for modern, complex System on Chip (SoC) designs, is growing on an unimaginable scale. In the past, it was possible to fit an...
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What is VLSI CAD and EDA?: Electronic Design Automation
All electronic devices that underpin modern society—smartphones, computers, automobiles, AI servers, and more—cannot exist without semiconductor chips. ...
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What is Tape Out in VLSI?
Do you have a semiconductor design engineer in your family? Before planning your Vacance? ask them for their 'Tape out' schedule. The term “tape-out” harks...