Founder of VLSI Korea. Staff Engineer at Synopsys — STA and physical-design methodology for advanced-node tape-outs. EE BS·MS · MBA. Writes from Seoul.
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Multi-Project Wafer (MPW) is a service that allows various semiconductor designs to be fabricated on a single wafer. Think of it like a "variety pizza"—instead of ordering a full pizza with just one topping, an MPW wafer combines multiple different designs from various teams onto a single
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Chip design, particularly for modern, complex System on Chip (SoC) designs, is growing on an unimaginable scale. In the past, it was possible to fit an entire design into a single Verilog netlist and process it with an EDA tool. Now, that approach leads to several problems. Massive Designs, New
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Introduction Engineering, unlike pure science, incorporates an additional crucial variable: profitability. The decision to mass-produce semiconductors hinges entirely on whether it can be done profitably. As of 2024/2025, how far have semiconductor manufacturing processes advanced? Are we at 3nm, 2nm, or 1.8nm? We have reached 0.7nm. IMEC
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All electronic devices that underpin modern society—smartphones, computers, automobiles, AI servers, and more—cannot exist without semiconductor chips. These tiny chips integrate billions of microscopic transistors onto a single piece of silicon, a highly integrated technology known as Very Large Scale Integration (VLSI). VLSI is not merely a continuation
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Smartphones, cars, and home appliances. The pulsating heart of these advanced devices, nestled in your hand or woven into your daily life, is often a tiny semiconductor chip. This small marvel enables an unimaginable array of complex functionalities. But did you know that the birth of such a "magical&
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Do you have a semiconductor design engineer in your family? Before planning your Vacance? ask them for their 'Tape out' schedule. The term “tape-out” harks back to the 1970s when engineers recorded design data on magnetic tapes and physically shipped them to foundries (Tapeout Origin). These tapes held
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Introduction The memory hierarchy is a cornerstone of modern computer architecture, enabling systems to balance the competing demands of speed, capacity, and cost. From ultra-fast registers to high-capacity hard disk drives (HDDs), each level of the hierarchy is optimized for specific performance characteristics. However, the growing disparity between processor and
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1. Introduction to Physical Verification in VLSI Design Physical verification is a critical step in the VLSI design flow, ensuring that the integrated circuit (IC) layout adheres to the manufacturing constraints defined by the foundry. Among the various checks performed, Design Rule Checking (DRC) is a cornerstone of physical verification,
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The High Bandwidth Memory (HBM) roadmap from HBM4 to HBM8 represents a transformative leap in memory architecture to meet the escalating demands of AI supercomputing, particularly for large language models (LLMs), generative AI, and eventual AGI/ASI systems. HBM4 (2026, NVIDIA Rubin, AMD MI400) * Specifications: 8Gbps (HBM4e: 10Gbps), 2048 I/
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Introduction to Semiconductor Yield In Very Large Scale Integration (VLSI) manufacturing, yield is a cornerstone metric that quantifies the proportion of functional integrated circuits (ICs) produced from a silicon wafer. Defined as the ratio of good chips to total chips, yield directly influences the economic viability of semiconductor production. The
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소개 Latch-based design is used in digital semiconductor design. Cell Transistor count D Latch 12~16 D Flip-Flop 18~32 Compared to Flip-Flop-based design, it offers the advantage of reduced transistor count, which impacts power and area. A key benefit of latches is timing flexibility through time borrowing. However, Flip-Flops
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Executive Summary The Trump administration's recent export control measures targeting Electronic Design Automation (EDA) software represent a paradigm shift in semiconductor geopolitics, fundamentally altering the landscape of global chip design capabilities. This comprehensive analysis examines the technical, economic, and strategic implications of restricting Synopsys, Cadence, and Siemens EDA