Clock Tree Synthesis (CTS) is a key step in physical design to evenly distribute the clock signal from the clock source to all flip-flops (FFs) on the chip. The goal is to minimize Clock Skew and control Insertion Delay to maximize timing margins.
Why is CTS necessary?
Large chips have hundreds of millions of flip-flops, all of which have physically different position coordinates. Semiconductor designs rely on flip-flops to move in time with the clock edge, so if possible, all flip-flops should move at the same time to make the design easier to control.
3 key concepts of CTS
1️⃣ Clock Skew
Clock Skew is the difference in arrival time between a flip-flop and another flip-flop:
- Clock Skew = T_arrival(FF1) - T_arrival(earliest FF2)
- Example: - FF_A receives clock at 1000ps - FF_B receives clock at 1050ps - Clock Skew = 1050ps - 1000ps = 50ps
2️⃣ Clock Latency
Latency is the absolute signal propagation time from the clock source to each flip-flop:
Insertion Delay (Latency) = Total delay from clock source (PLL) to register
In other words, skew is the difference between Latency.
3️⃣ Useful Skew
In addition to some techniques to make the clock arrival time different. This is called Useful Skew, a technique that modifies the clock path to close the timing.
Clock Tree Topologies - H-Tree and Fishebone
The most popular topology for Clock Tree is the H-Tree structure. It branches recursively from the root, with distances and loads evenly distributed in the scare phase. This automatically balances the path length and delay to all leaf nodes (flip-flops).
Other approaches include Mesh and Fishbone, where the Fishbone topology has branches branching out in either direction from a central "spine" line.