![[Synopsys Free Webinar] Why RTL Simulation Isn't Enough for AI Chip Verification: Rebellions·Synopsys HAV Success Story](https://storage.ghost.io/c/e0/1d/e01dab3f-8599-4f20-85b3-3b2507a10672/content/images/size/w1200/2026/04/-------------2.png)
Synopsys is hosting a free webinar for the first time in a long while. The topic is HAV — one of the hottest subjects in the industry right now. Register first, then tune in while you work. 😄
The simulation is nowhere near done. But the tape-out deadline is closing in.
Anyone who has worked on chip design has been through this at least once. You can't go home. You spend every holiday at the office. You set your alarm to match the EDA tool runtime and sleep in between.
You kick off an RTL simulation, and days pass without it finishing. Eventually you cut it with a timeout and tell yourself, "We hit the coverage targets — we did what we had to do." Whether that call was right or wrong only becomes clear when the first silicon sample arrives.
The 2024 Wilson Research Group survey confirms that anxiety is well-founded. First-silicon success rates stand at just 14% — the lowest in 20 years of tracking. That means 8 to 9 out of every 10 tapeouts require a respin.
Ed Sperling
At advanced process nodes, a silicon re-spin is not just a cost issue. Mask set costs alone run into tens of millions of dollars at 3nm. Add a 6–12 month schedule slip on top of that. For a startup, it's quite literally an existential threat.
So how did we get here?
Chip bugs can no longer be caught by RTL simulation alone.
Not long ago, SoCs were in the tens-of-millions-of-gates range. Verification targets were relatively well-defined. You'd partition by subsystem in an HPDF design, run simulations, catch corner cases, then run vectors at the top level and check for pass.
Today is different.
Mainstream designs already exceed 15 billion gates, and data-center AI chips are approaching 50 billion. Verification scope has exploded — cache coherency, NoC traffic, multi-die interfaces, and HW/SW interactions all have to be verified.
The more critical issue is that where bugs surface has fundamentally changed.
Today's critical bugs don't show up in standalone RTL simulation. They emerge during OS boot, driver initialization, and real AI workload execution. Reproducing them in simulation requires trillions of cycles — simply not feasible before tapeout.
There's only one answer. Accelerate verification. That's what HAV — Hardware-Assisted Verification — is all about.
What is HAV? (Hardware-Assisted Verification)
HAV maps the RTL under verification onto dedicated hardware and runs it there. There are two major approaches.
FPGA Prototyping (Synopsys HAPS) runs on real FPGAs at tens of MHz. It excels at HW/SW integration verification and software bring-up.
Emulation (Synopsys ZeBu) preserves verification-friendly features like signal visibility, debug, and assertions. The key advantage is being hundreds to thousands of times faster than simulation while still enabling deep debug. All three EDA majors are investing heavily in emulation right now.
The industry is rapidly moving toward ZeBu emulation as the centerpiece of AI chip verification.
Why Rebellions Chose ZeBu to Verify REBEL-Quad
Founded in 2020, Rebellions is a Korean AI semiconductor startup valued at approximately $2.5B as of 2026, with around $1B in cumulative funding — a true unicorn. ARM invested directly, while SK Hynix, SK Telecom, Samsung Ventures, and KT are among its shareholders. It achieved the first large-scale commercial deployment of a domestically developed Korean AI chip by supplying ATOM chips to KT Cloud.
I personally worked on the Top STA for the first-generation ATOM chip.
Even back then it was no easy task — but the scale and complexity of REBEL-Quad are in an entirely different league. (Take a look at the spec sheet; comparing the Rebellions chip against competitors reveals specs at or near the top of the industry. PCIe lane count and bandwidth alone signal their ambition to lead.)
With a 4-chiplet architecture, UCIe interfaces, and HBM3E attached, the verification complexity goes far beyond what gate count alone can express.
And Rebellions is not just an NPU design house — it's an AI systems company. Verification doesn't stop at the chip; the scope extends to Linux, drivers, runtime, compilers, PyTorch, Hugging Face, and actual customer LLM models.
Their latest chip REBEL-Quad embodies that complexity in full.
It's the world's first commercially available UCIe-based AI accelerator, connecting four identical NPU chiplets via UCIe-Advanced interfaces. Built on Samsung 4nm, with 144GB HBM3E and 4.8TB/s memory bandwidth. It delivers 2 PFLOPS (FP8) at 600W — 1.6× the throughput of a GPU with 50% lower power consumption, and 3.2× better efficiency by TPS/W.
Rebellions combined Synopsys ZeBu and Virtualizer for verifying this chip. The way they used these tools together is particularly interesting.
For functional verification, they ran full ZeBu mapping; for rapid software stack development, they switched to the Virtualizer virtual prototype. Each tool was used flexibly based on the task at hand. This let them run LLMs in the pre-silicon stage, enter prompts from the host, and verify token acceleration within the full system context.
The results speak for themselves.
First silicon → live demo in 5 weeks. And ZeBu's performance predictions matched actual silicon at 98% accuracy.
In the words of Rebellions CTO Oh Jinwook: "ZeBu led the emulation of this project to success, thanks to its speed, capacity, and the support of the Synopsys team."
Frank Schirrmeister
For a semiconductor company, time is a matter of survival. One silicon respin can cost hundreds of millions of dollars and months of schedule.
Spending more on verification is justified if it improves time-to-market and verification accuracy. Rebellions' decision to use ZeBu was both a technical choice and a business survival strategy.
What's New with Synopsys HAV
At Converge 2026 in March, Synopsys announced a comprehensive update to its HAV portfolio.
The centerpiece is the concept of "SW Defined HAV" — a strategy to continuously improve performance, functionality, and longevity through software updates alone, without replacing hardware. Since 2023, software updates alone have delivered up to 2× performance improvement, 3× faster time-to-model, and 4–8× higher debug throughput.
On the platform side, the new HAPS-200 12F and ZeBu-200 12F have launched. As successors to the previous 6-FPGA platform, they feature an EP-Ready architecture that allows switching between emulation and prototyping in software on the same hardware. ZeBu Server 5 for large designs has doubled capacity as a modular HAV system.
If you're already running an HAV system — the practical takeaway from this announcement is that you can access all these capabilities through a software update, with no new hardware required.
April 29: Webinar with Rebellions' Verification Leader
You'll have the chance to hear directly from the people who built all of this.
I'll be attending as well, as an STA engineer. I'd strongly encourage engineers and professors in chip design and hardware to join. This is the first webinar Synopsys has held in a long time, and Rebellions — with their world-class HAV experience — has prepared a lot of great content.
Topic: Synopsys Software-Defined HAV for AI-Era Chip Design
📅 Wednesday, April 29, 2026, 2:00 – 3:00 PM KST 📍 Zoom Online
👉 Free Registration Page
Speakers
- Park Sang-gyu — Rebellions Verification Leader.
- Ph.D., Seoul National University
- 15 years at Samsung Semiconductor Exynos team (led multimedia IP and NPU verification)
- Since 2022, leads REBEL-Quad multi-chiplet SoC-level verification at Rebellions.
- Lee Gang-wook — Synopsys ZeBu AE Principal Engineer
- Former SK Hynix engineer
- Joined Synopsys in 2017; has since provided dedicated ZeBu solution support for Samsung Electronics and domestic AI startups.
Session Topics
- Latest software-defined HAV features presented at Converge 2026
- ZeBu emulation key use cases and solutions
- Rebellions' custom XTOR (transactor) development strategy — insights on building an integrated testbench
- Hands-on experience building with the custom XTOR solution
What makes the Rebellions presentation especially noteworthy is this: XTORs (transactors) are the key performance bottleneck in emulation — and hearing how a startup designed and integrated their own custom XTOR is the kind of insight you simply cannot buy anywhere else.
If any of the following describes you, this is a must-attend event!
SoC design/verification engineers / SoC Architects / ASIC design/verification engineers / HW & SW developers / Emulation & Virtualizer platform engineers
For the latest HAV resources, visit the Synopsys free webinar page: